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Commit | Line | Data |
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887e2ec9 | 1 | /* |
02388983 SR |
2 | * (C) Copyright 2006 |
3 | * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com | |
4 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
5 | * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com | |
6 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
7 | * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com | |
8 | * | |
07b7b003 | 9 | * (C) Copyright 2006-2007 |
887e2ec9 SR |
10 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
11 | * | |
1a459660 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
887e2ec9 SR |
13 | */ |
14 | ||
02388983 SR |
15 | /* define DEBUG for debug output */ |
16 | #undef DEBUG | |
17 | ||
887e2ec9 SR |
18 | #include <common.h> |
19 | #include <asm/processor.h> | |
02388983 | 20 | #include <asm/io.h> |
b36df561 | 21 | #include <asm/ppc440.h> |
887e2ec9 | 22 | |
02388983 | 23 | /*-----------------------------------------------------------------------------+ |
ce3902e1 LJ |
24 | * Prototypes |
25 | *-----------------------------------------------------------------------------*/ | |
26 | extern int denali_wait_for_dlllock(void); | |
27 | extern void denali_core_search_data_eye(void); | |
02388983 | 28 | |
f544ff66 | 29 | #if defined(CONFIG_NAND_SPL) |
a47a12be | 30 | /* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big |
f544ff66 SR |
31 | * for the 4k NAND boot image so define bus_frequency to 133MHz here |
32 | * which is save for the refresh counter setup. | |
33 | */ | |
17c1b0e8 | 34 | #define get_bus_freq(val) 133333333 |
f544ff66 SR |
35 | #endif |
36 | ||
887e2ec9 SR |
37 | /************************************************************************* |
38 | * | |
39 | * initdram -- 440EPx's DDR controller is a DENALI Core | |
40 | * | |
41 | ************************************************************************/ | |
9973e3c6 | 42 | phys_size_t initdram (int board_type) |
887e2ec9 | 43 | { |
d873133f SR |
44 | #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \ |
45 | defined(CONFIG_NAND_SPL) | |
07b7b003 SR |
46 | ulong speed = get_bus_freq(0); |
47 | ||
887e2ec9 SR |
48 | mtsdram(DDR0_02, 0x00000000); |
49 | ||
887e2ec9 SR |
50 | mtsdram(DDR0_00, 0x0000190A); |
51 | mtsdram(DDR0_01, 0x01000000); | |
52 | mtsdram(DDR0_03, 0x02030602); | |
07b7b003 SR |
53 | mtsdram(DDR0_04, 0x0A020200); |
54 | mtsdram(DDR0_05, 0x02020308); | |
55 | mtsdram(DDR0_06, 0x0102C812); | |
887e2ec9 | 56 | mtsdram(DDR0_07, 0x000D0100); |
07b7b003 | 57 | mtsdram(DDR0_08, 0x02430001); |
887e2ec9 | 58 | mtsdram(DDR0_09, 0x00011D5F); |
ee86fd15 | 59 | mtsdram(DDR0_10, 0x00000100); |
887e2ec9 SR |
60 | mtsdram(DDR0_11, 0x0027C800); |
61 | mtsdram(DDR0_12, 0x00000003); | |
62 | mtsdram(DDR0_14, 0x00000000); | |
63 | mtsdram(DDR0_17, 0x19000000); | |
64 | mtsdram(DDR0_18, 0x19191919); | |
65 | mtsdram(DDR0_19, 0x19191919); | |
66 | mtsdram(DDR0_20, 0x0B0B0B0B); | |
67 | mtsdram(DDR0_21, 0x0B0B0B0B); | |
68 | mtsdram(DDR0_22, 0x00267F0B); | |
69 | mtsdram(DDR0_23, 0x00000000); | |
70 | mtsdram(DDR0_24, 0x01010002); | |
f544ff66 | 71 | if (speed > 133333334) |
07b7b003 SR |
72 | mtsdram(DDR0_26, 0x5B26050C); |
73 | else | |
74 | mtsdram(DDR0_26, 0x5B260408); | |
887e2ec9 SR |
75 | mtsdram(DDR0_27, 0x0000682B); |
76 | mtsdram(DDR0_28, 0x00000000); | |
77 | mtsdram(DDR0_31, 0x00000000); | |
78 | mtsdram(DDR0_42, 0x01000006); | |
07b7b003 SR |
79 | mtsdram(DDR0_43, 0x030A0200); |
80 | mtsdram(DDR0_44, 0x00000003); | |
887e2ec9 SR |
81 | mtsdram(DDR0_02, 0x00000001); |
82 | ||
ce3902e1 | 83 | denali_wait_for_dlllock(); |
887e2ec9 SR |
84 | #endif /* #ifndef CONFIG_NAND_U_BOOT */ |
85 | ||
02388983 SR |
86 | #ifdef CONFIG_DDR_DATA_EYE |
87 | /* -----------------------------------------------------------+ | |
88 | * Perform data eye search if requested. | |
89 | * ----------------------------------------------------------*/ | |
ce3902e1 | 90 | denali_core_search_data_eye(); |
02388983 SR |
91 | #endif |
92 | ||
d5a163d6 SR |
93 | /* |
94 | * Clear possible errors resulting from data-eye-search. | |
95 | * If not done, then we could get an interrupt later on when | |
96 | * exceptions are enabled. | |
97 | */ | |
98 | set_mcsr(get_mcsr()); | |
99 | ||
6d0f6bcf | 100 | return (CONFIG_SYS_MBYTES_SDRAM << 20); |
887e2ec9 | 101 | } |