]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/amcc/taihu/taihu.c
Fix incorrect use of getenv() before relocation
[people/ms/u-boot.git] / board / amcc / taihu / taihu.c
CommitLineData
d4024bb7
JO
1/*
2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2005-2007
6 * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26#include <common.h>
27#include <command.h>
28#include <asm/processor.h>
29#include <asm/io.h>
30#include <spi.h>
10efa024 31#include <netdev.h>
09887762 32#include <asm/ppc4xx-gpio.h>
d4024bb7
JO
33
34extern int lcd_init(void);
35
36/*
37 * board_early_init_f
38 */
39int board_early_init_f(void)
40{
41 lcd_init();
42
952e7760
SR
43 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
44 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
45 mtdcr(UIC0CR, 0x00000000);
46 mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
47 mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
48 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
49 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
d4024bb7 50
d1c3b275
SR
51 mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
52 mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
d4024bb7 53
779e9751
SR
54 /*
55 * Configure CPC0_PCI to enable PerWE as output
56 * and enable the internal PCI arbiter
57 */
d1c3b275 58 mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
779e9751 59
d4024bb7
JO
60 return 0;
61}
62
63/*
64 * Check Board Identity:
65 */
66int checkboard(void)
67{
f0c0b3a9
WD
68 char buf[64];
69 int i = getenv_f("serial#", buf, sizeof(buf));
d4024bb7
JO
70
71 puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
72
f0c0b3a9 73 if (i > 0) {
d4024bb7 74 puts(", serial# ");
f0c0b3a9 75 puts(buf);
d4024bb7
JO
76 }
77 putc('\n');
78
79 return 0;
80}
81
54841ab5 82static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
d4024bb7
JO
83{
84 char stat;
85 int i;
86
87 stat = in_8((u8 *) CPLD_REG0_ADDR);
88 printf("SW2 status: ");
89 for (i=0; i<4; i++) /* 4-position */
90 printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
91 printf("\n");
92 return 0;
93}
94
95U_BOOT_CMD (
96 sw2_stat, 1, 1, do_sw_stat,
2fb2604d 97 "show status of switch 2",
a89c33db
WD
98 ""
99);
d4024bb7 100
54841ab5 101static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
d4024bb7
JO
102{
103 int led_no;
104
47e26b1b
WD
105 if (argc != 3)
106 return cmd_usage(cmd_tp);
d4024bb7
JO
107
108 led_no = simple_strtoul(argv[1], NULL, 16);
47e26b1b
WD
109 if (led_no != 1 && led_no != 2)
110 return cmd_usage(cmd_tp);
d4024bb7
JO
111
112 if (strcmp(argv[2],"off") == 0x0) {
113 if (led_no == 1)
114 gpio_write_bit(30, 1);
115 else
116 gpio_write_bit(31, 1);
117 } else if (strcmp(argv[2],"on") == 0x0) {
118 if (led_no == 1)
119 gpio_write_bit(30, 0);
120 else
121 gpio_write_bit(31, 0);
122 } else {
47e26b1b 123 return cmd_usage(cmd_tp);
d4024bb7
JO
124 }
125
126 return 0;
127}
128
129U_BOOT_CMD (
130 led_ctl, 3, 1, do_led_ctl,
2fb2604d 131 "make led 1 or 2 on or off",
d4024bb7 132 "<led_no> <on/off> - make led <led_no> on/off,\n"
a89c33db
WD
133 "\tled_no is 1 or 2"
134);
d4024bb7
JO
135
136#define SPI_CS_GPIO0 0
137#define SPI_SCLK_GPIO14 14
138#define SPI_DIN_GPIO15 15
139#define SPI_DOUT_GPIO16 16
140
141void spi_scl(int bit)
142{
143 gpio_write_bit(SPI_SCLK_GPIO14, bit);
144}
145
146void spi_sda(int bit)
147{
148 gpio_write_bit(SPI_DOUT_GPIO16, bit);
149}
150
151unsigned char spi_read(void)
152{
772003e4 153 return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15);
d4024bb7
JO
154}
155
d255bb0e 156int spi_cs_is_valid(unsigned int bus, unsigned int cs)
d4024bb7 157{
d255bb0e 158 return bus == 0 && cs == 0;
d4024bb7
JO
159}
160
d255bb0e
HS
161void spi_cs_activate(struct spi_slave *slave)
162{
163 gpio_write_bit(SPI_CS_GPIO0, 1);
164}
d4024bb7 165
d255bb0e
HS
166void spi_cs_deactivate(struct spi_slave *slave)
167{
168 gpio_write_bit(SPI_CS_GPIO0, 0);
169}
d4024bb7
JO
170
171#ifdef CONFIG_PCI
172static unsigned char int_lines[32] = {
173 29, 30, 27, 28, 29, 30, 25, 27,
174 29, 30, 27, 28, 29, 30, 27, 28,
175 29, 30, 27, 28, 29, 30, 27, 28,
176 29, 30, 27, 28, 29, 30, 27, 28};
177
178static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
179{
180 unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
181
182 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
183}
184
185int pci_pre_init(struct pci_controller *hose)
186{
187 hose->fixup_irq = taihu_pci_fixup_irq;
188 return 1;
189}
190#endif /* CONFIG_PCI */
10efa024
BW
191
192int board_eth_init(bd_t *bis)
193{
cef0efaf 194 cpu_eth_init(bis);
10efa024
BW
195 return pci_eth_init(bis);
196}