[people/ms/u-boot.git] / board / amcc / yosemite / yosemite.c

/*
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <spd_sdram.h>

extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/

int board_early_init_f(void)
{
	register uint reg;

	/*--------------------------------------------------------------------
	 * Setup the external bus controller/chip selects
	 *-------------------------------------------------------------------*/
	mtdcr(ebccfga, xbcfg);
	reg = mfdcr(ebccfgd);
	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */

	mtebc(pb0ap, 0x03017300);	/* FLASH/SRAM */
	mtebc(pb0cr, 0xfc0da000);	/* BAS=0xfc0 64MB r/w 16-bit */

	mtebc(pb1ap, 0x00000000);
	mtebc(pb1cr, 0x00000000);

	mtebc(pb2ap, 0x04814500);
	/*CPLD*/ mtebc(pb2cr, 0x80018000);	/*BAS=0x800 1MB r/w 8-bit */

	mtebc(pb3ap, 0x00000000);
	mtebc(pb3cr, 0x00000000);

	mtebc(pb4ap, 0x00000000);
	mtebc(pb4cr, 0x00000000);

	mtebc(pb5ap, 0x00000000);
	mtebc(pb5cr, 0x00000000);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr(uic0sr, 0xffffffff);	/* clear all */
	mtdcr(uic0er, 0x00000000);	/* disable all */
	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic0sr, 0xffffffff);	/* clear all */

	mtdcr(uic1sr, 0xffffffff);	/* clear all */
	mtdcr(uic1er, 0x00000000);	/* disable all */
	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic1sr, 0xffffffff);	/* clear all */

	/*--------------------------------------------------------------------
	 * Setup the GPIO pins
	 *-------------------------------------------------------------------*/
	/*CPLD cs */
	/*setup Address lines for flash sizes larger than 16Meg. */
	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);

	/*setup emac */
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);

	/*UART1 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);

	/*setup USB 2.0 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);

	/*--------------------------------------------------------------------
	 * Setup other serial configuration
	 *-------------------------------------------------------------------*/
	mfsdr(sdr_pci0, reg);
	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
	mtsdr(sdr_pfc0, 0x00003e00);	/* Pin function */
	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins */

	/*clear tmrclk divisor */
	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;

	/*enable ethernet */
	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;

	/*enable usb 1.1 fs device and remove usb 2.0 reset */
	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;

	/*get rid of flash write protect */
	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;

	return 0;
}

int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;
	uint pbcr;
	int size_val = 0;

	/* Re-do sizing to get full correct info */
	mtdcr(ebccfga, pb0cr);
	pbcr = mfdcr(ebccfgd);
	switch (gd->bd->bi_flashsize) {
	case 1 << 20:
		size_val = 0;
		break;
	case 2 << 20:
		size_val = 1;
		break;
	case 4 << 20:
		size_val = 2;
		break;
	case 8 << 20:
		size_val = 3;
		break;
	case 16 << 20:
		size_val = 4;
		break;
	case 32 << 20:
		size_val = 5;
		break;
	case 64 << 20:
		size_val = 6;
		break;
	case 128 << 20:
		size_val = 7;
		break;
	}
	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
	mtdcr(ebccfga, pb0cr);
	mtdcr(ebccfgd, pbcr);

	/* Monitor protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    -CFG_MONITOR_LEN,
			    0xffffffff,
			    &flash_info[0]);

	return 0;
}

int checkboard(void)
{
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);

	printf("Board: AMCC YOSEMITE\n");
	printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
	printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
	printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
	printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);


	return (0);
}

/*************************************************************************
 *  sdram_init -- doesn't use serial presence detect.
 *
 *  Assumes:    256 MB, ECC, non-registered
 *              PLB @ 133 MHz
 *
 ************************************************************************/
void sdram_init(void)
{
	register uint reg;

	/*--------------------------------------------------------------------
	 * Setup some default
	 *------------------------------------------------------------------*/
	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
	mtsdram(mem_clktr, 0x40000000);	/* ?? */
	mtsdram(mem_wddctr, 0x40000000);	/* ?? */

	/*clear this first, if the DDR is enabled by a debugger
	   then you can not make changes. */
	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */

	/*--------------------------------------------------------------------
	 * Setup for board-specific specific mem
	 *------------------------------------------------------------------*/
	/*
	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
	 */
	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
	mtsdram(mem_b1cr, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */

	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
	mtsdram(mem_tr1, 0x8080080b);	/* ?? */
	mtsdram(mem_rtr, 0x04080000);	/* ?? */
	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
	mtsdram(mem_cfg0, 0x34000000);	/* Disable EEC */
	udelay(400);		/* Delay 200 usecs (min)            */

	/*--------------------------------------------------------------------
	 * Enable the controller, then wait for DCEN to complete
	 *------------------------------------------------------------------*/
	mtsdram(mem_cfg0, 0x84000000);	/* Enable */

	for (;;) {
		mfsdram(mem_mcsts, reg);
		if (reg & 0x80000000)
			break;
	}
}

/*************************************************************************
 *  long int initdram
 *
 ************************************************************************/
long int initdram(int board)
{
	sdram_init();
	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);	/* return bytes */
}

#if defined(CFG_DRAM_TEST)
int testdram(void)
{
	unsigned long *mem = (unsigned long *)0;
	const unsigned long kend = (1024 / sizeof(unsigned long));
	unsigned long k, n;

	mtmsr(0);

	for (k = 0; k < CFG_KBYTES_SDRAM;
	     ++k, mem += (1024 / sizeof(unsigned long))) {
		if ((k & 1023) == 0) {
			printf("%3d MB\r", k / 1024);
		}

		memset(mem, 0xaaaaaaaa, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0xaaaaaaaa) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}

		memset(mem, 0x55555555, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0x55555555) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}
	}
	printf("SDRAM test passes\n");
	return 0;
}
#endif

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
	unsigned long strap;
	unsigned long addr;

	/*--------------------------------------------------------------------------+
	 *	Bamboo is always configured as the host & requires the
	 *	PCI arbiter to be enabled.
	 *--------------------------------------------------------------------------*/
	mfsdr(sdr_sdstp1, strap);
	if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
		printf("PCI: SDR0_STRP1[PAE] not set.\n");
		printf("PCI: Configuration aborted.\n");
		return 0;
	}

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB3 devices to 0.
	  | Set PLB3 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp1, addr);
	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb3_acr);
	mtdcr(plb3_acr, addr | 0x80000000);

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB4 devices to 0.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp0, addr);
	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
	mtdcr(plb4_acr, addr);

	/*-------------------------------------------------------------------------+
	  | Set Nebula PLB4 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	/* Segment0 */
	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
	mtdcr(plb0_acr, addr);

	/* Segment1 */
	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
	mtdcr(plb1_acr, addr);

	return 1;
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
	/*--------------------------------------------------------------------------+
	 * Set up Direct MMIO registers
	 *--------------------------------------------------------------------------*/
	/*--------------------------------------------------------------------------+
	  | PowerPC440 EP PCI Master configuration.
	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
	  |   Use byte reversed out routines to handle endianess.
	  | Make this region non-prefetchable.
	  +--------------------------------------------------------------------------*/
	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */

	/*--------------------------------------------------------------------------+
	 * Set up Configuration registers
	 *--------------------------------------------------------------------------*/

	/* Program the board's subsystem id/vendor id */
	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
			      CFG_PCI_SUBSYS_VENDORID);
	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);

	/* Configure command register as bus master */
	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);

	/* 240nS PCI clock */
	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);

	/* No error reporting */
	pci_write_config_word(0, PCI_ERREN, 0);

	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);

}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

/*************************************************************************
 *  pci_master_init
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
	unsigned short temp_short;

	/*--------------------------------------------------------------------------+
	  | Write the PowerPC440 EP PCI Configuration regs.
	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
	  +--------------------------------------------------------------------------*/
	pci_read_config_word(0, PCI_COMMAND, &temp_short);
	pci_write_config_word(0, PCI_COMMAND,
			      temp_short | PCI_COMMAND_MASTER |
			      PCI_COMMAND_MEMORY);
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */

/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
	/* Bamboo is always configured as host. */
	return (1);
}
#endif				/* defined(CONFIG_PCI) */

/*************************************************************************
 *  hw_watchdog_reset
 *
 *	This routine is called to reset (keep alive) the watchdog timer
 *
 ************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{

}
#endif
Commit	Line	Data
c157d8e2 SR	1	/*
	2	*
	3	* See file CREDITS for list of people who contributed to this
	4	* project.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include <common.h>
84286386	23	#include <ppc4xx.h>
c157d8e2 SR	24	#include <asm/processor.h>
	25	#include <spd_sdram.h>
	26
84286386 SR	27	extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
84286386 SR	28
c157d8e2 SR	29	int board_early_init_f(void)
	30	{
	31	register uint reg;
	32
	33	/*--------------------------------------------------------------------
	34	* Setup the external bus controller/chip selects
	35	-------------------------------------------------------------------/
	36	mtdcr(ebccfga, xbcfg);
	37	reg = mfdcr(ebccfgd);
	38	mtdcr(ebccfgd, reg \| 0x04000000); /* Set ATC */
	39
	40	mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
84286386	41	mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
c157d8e2 SR	42
	43	mtebc(pb1ap, 0x00000000);
	44	mtebc(pb1cr, 0x00000000);
	45
	46	mtebc(pb2ap, 0x04814500);
	47	/CPLD/ mtebc(pb2cr, 0x80018000); /BAS=0x800 1MB r/w 8-bit /
	48
	49	mtebc(pb3ap, 0x00000000);
	50	mtebc(pb3cr, 0x00000000);
	51
	52	mtebc(pb4ap, 0x00000000);
	53	mtebc(pb4cr, 0x00000000);
	54
	55	mtebc(pb5ap, 0x00000000);
	56	mtebc(pb5cr, 0x00000000);
	57
	58	/*--------------------------------------------------------------------
	59	* Setup the interrupt controller polarities, triggers, etc.
	60	-------------------------------------------------------------------/
	61	mtdcr(uic0sr, 0xffffffff); /* clear all */
	62	mtdcr(uic0er, 0x00000000); /* disable all */
	63	mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
	64	mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
	65	mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
	66	mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
	67	mtdcr(uic0sr, 0xffffffff); /* clear all */
	68
	69	mtdcr(uic1sr, 0xffffffff); /* clear all */
	70	mtdcr(uic1er, 0x00000000); /* disable all */
	71	mtdcr(uic1cr, 0x00000000); /* all non-critical */
	72	mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
	73	mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
	74	mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
	75	mtdcr(uic1sr, 0xffffffff); /* clear all */
	76
	77	/*--------------------------------------------------------------------
	78	* Setup the GPIO pins
	79	-------------------------------------------------------------------/
	80	/CPLD cs /
	81	/setup Address lines for flash sizes larger than 16Meg. /
	82	out32(GPIO0_OSRL, in32(GPIO0_OSRL) \| 0x40010000);
	83	out32(GPIO0_TSRL, in32(GPIO0_TSRL) \| 0x40010000);
	84	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) \| 0x40000000);
	85
	86	/setup emac /
	87	out32(GPIO0_TCR, in32(GPIO0_TCR) \| 0xC080);
	88	out32(GPIO0_TSRL, in32(GPIO0_TSRL) \| 0x40);
	89	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) \| 0x55);
	90	out32(GPIO0_OSRH, in32(GPIO0_OSRH) \| 0x50004000);
	91	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) \| 0x00440000);
	92
	93	/UART1 /
	94	out32(GPIO1_TCR, in32(GPIO1_TCR) \| 0x02000000);
	95	out32(GPIO1_OSRL, in32(GPIO1_OSRL) \| 0x00080000);
	96	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) \| 0x00010000);
	97
	98	/setup USB 2.0 /
	99	out32(GPIO1_TCR, in32(GPIO1_TCR) \| 0xc0000000);
	100	out32(GPIO1_OSRL, in32(GPIO1_OSRL) \| 0x50000000);
	101	out32(GPIO0_TCR, in32(GPIO0_TCR) \| 0xf);
	102	out32(GPIO0_OSRH, in32(GPIO0_OSRH) \| 0xaa);
	103	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) \| 0x00000500);
	104
	105	/*--------------------------------------------------------------------
106	* Setup other serial configuration
107	-------------------------------------------------------------------/
108	mfsdr(sdr_pci0, reg);
109	mtsdr(sdr_pci0, 0x80000000 \| reg); /* PCI arbiter enabled */
110	mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
111	mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
112
113	/clear tmrclk divisor /
114	(unsigned char )(CFG_BCSR_BASE \| 0x04) = 0x00;
115
116	/enable ethernet /
117	(unsigned char )(CFG_BCSR_BASE \| 0x08) = 0xf0;
118
119	/enable usb 1.1 fs device and remove usb 2.0 reset /
120	(unsigned char )(CFG_BCSR_BASE \| 0x09) = 0x00;
121
122	/get rid of flash write protect /
123	(unsigned char )(CFG_BCSR_BASE \| 0x07) = 0x40;
124
125	return 0;
126	}
127
84286386 SR	128	int misc_init_r (void)
	129	{
	130	DECLARE_GLOBAL_DATA_PTR;
	131	uint pbcr;
	132	int size_val = 0;
	133
	134	/* Re-do sizing to get full correct info */
	135	mtdcr(ebccfga, pb0cr);
	136	pbcr = mfdcr(ebccfgd);
	137	switch (gd->bd->bi_flashsize) {
	138	case 1 << 20:
	139	size_val = 0;
	140	break;
	141	case 2 << 20:
	142	size_val = 1;
	143	break;
	144	case 4 << 20:
	145	size_val = 2;
	146	break;
	147	case 8 << 20:
	148	size_val = 3;
	149	break;
	150	case 16 << 20:
	151	size_val = 4;
	152	break;
	153	case 32 << 20:
	154	size_val = 5;
	155	break;
	156	case 64 << 20:
	157	size_val = 6;
	158	break;
	159	case 128 << 20:
	160	size_val = 7;
	161	break;
	162	}
	163	pbcr = (pbcr & 0x0001ffff) \| gd->bd->bi_flashstart \| (size_val << 17);
	164	mtdcr(ebccfga, pb0cr);
	165	mtdcr(ebccfgd, pbcr);
	166
	167	/* Monitor protection ON by default */
	168	(void)flash_protect(FLAG_PROTECT_SET,
	169	-CFG_MONITOR_LEN,
	170	0xffffffff,
	171	&flash_info[0]);
	172
	173	return 0;
	174	}
	175
c157d8e2 SR	176	int checkboard(void)
	177	{
	178	sys_info_t sysinfo;
	179
	180	get_sys_info(&sysinfo);
	181
	182	printf("Board: AMCC YOSEMITE\n");
	183	printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
	184	printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
	185	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
	186	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
	187	printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
	188	printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
84286386 SR	189
84286386 SR	190
c157d8e2 SR	191	return (0);
	192	}
	193
	194	/*************************************************************************
	195	* sdram_init -- doesn't use serial presence detect.
	196	*
	197	* Assumes: 256 MB, ECC, non-registered
	198	* PLB @ 133 MHz
	199	*
	200	************************************************************************/
	201	void sdram_init(void)
	202	{
	203	register uint reg;
	204
	205	/*--------------------------------------------------------------------
	206	* Setup some default
	207	------------------------------------------------------------------/
	208	mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
	209	mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
	210	mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
	211	mtsdram(mem_clktr, 0x40000000); /* ?? */
	212	mtsdram(mem_wddctr, 0x40000000); /* ?? */
	213
	214	/*clear this first, if the DDR is enabled by a debugger
	215	then you can not make changes. */
	216	mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
	217
	218	/*--------------------------------------------------------------------
	219	* Setup for board-specific specific mem
	220	------------------------------------------------------------------/
	221	/*
	222	* Following for CAS Latency = 2.5 @ 133 MHz PLB
	223	*/
	224	mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
	225	mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
	226
	227	mtsdram(mem_tr0, 0x410a4012); /* ?? */
	228	mtsdram(mem_tr1, 0x8080080b); /* ?? */
	229	mtsdram(mem_rtr, 0x04080000); /* ?? */
	230	mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
	231	mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
	232	udelay(400); /* Delay 200 usecs (min) */
	233
	234	/*--------------------------------------------------------------------
	235	* Enable the controller, then wait for DCEN to complete
	236	------------------------------------------------------------------/
	237	mtsdram(mem_cfg0, 0x84000000); /* Enable */
	238
	239	for (;;) {
	240	mfsdram(mem_mcsts, reg);
	241	if (reg & 0x80000000)
	242	break;
	243	}
	244	}
	245
	246	/*************************************************************************
	247	* long int initdram
	248	*
	249	************************************************************************/
	250	long int initdram(int board)
	251	{
	252	sdram_init();
	253	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
	254	}
255
256	#if defined(CFG_DRAM_TEST)
257	int testdram(void)
258	{
259	unsigned long mem = (unsigned long )0;
260	const unsigned long kend = (1024 / sizeof(unsigned long));
261	unsigned long k, n;
262
263	mtmsr(0);
264
265	for (k = 0; k < CFG_KBYTES_SDRAM;
266	++k, mem += (1024 / sizeof(unsigned long))) {
267	if ((k & 1023) == 0) {
268	printf("%3d MB\r", k / 1024);
269	}
270
271	memset(mem, 0xaaaaaaaa, 1024);
272	for (n = 0; n < kend; ++n) {
273	if (mem[n] != 0xaaaaaaaa) {
274	printf("SDRAM test fails at: %08x\n",
275	(uint) & mem[n]);
276	return 1;
277	}
278	}
279
280	memset(mem, 0x55555555, 1024);
281	for (n = 0; n < kend; ++n) {
282	if (mem[n] != 0x55555555) {
283	printf("SDRAM test fails at: %08x\n",
284	(uint) & mem[n]);
285	return 1;
286	}
287	}
288	}
289	printf("SDRAM test passes\n");
290	return 0;
291	}
292	#endif
293
294	/*************************************************************************
295	* pci_pre_init
296	*
297	* This routine is called just prior to registering the hose and gives
298	* the board the opportunity to check things. Returning a value of zero
299	* indicates that things are bad & PCI initialization should be aborted.
300	*
301	* Different boards may wish to customize the pci controller structure
302	* (add regions, override default access routines, etc) or perform
303	* certain pre-initialization actions.
304	*
305	************************************************************************/
306	#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
307	int pci_pre_init(struct pci_controller *hose)
308	{
309	unsigned long strap;
310	unsigned long addr;
311
312	/*--------------------------------------------------------------------------+
313	* Bamboo is always configured as the host & requires the
314	* PCI arbiter to be enabled.
315	--------------------------------------------------------------------------/
316	mfsdr(sdr_sdstp1, strap);
317	if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
318	printf("PCI: SDR0_STRP1[PAE] not set.\n");
319	printf("PCI: Configuration aborted.\n");
320	return 0;
321	}
322
323	/*-------------------------------------------------------------------------+
324	\| Set priority for all PLB3 devices to 0.
325	\| Set PLB3 arbiter to fair mode.
326	+-------------------------------------------------------------------------*/
327	mfsdr(sdr_amp1, addr);
328	mtsdr(sdr_amp1, (addr & 0x000000FF) \| 0x0000FF00);
329	addr = mfdcr(plb3_acr);
330	mtdcr(plb3_acr, addr \| 0x80000000);
331
332	/*-------------------------------------------------------------------------+
333	\| Set priority for all PLB4 devices to 0.
334	+-------------------------------------------------------------------------*/
335	mfsdr(sdr_amp0, addr);
336	mtsdr(sdr_amp0, (addr & 0x000000FF) \| 0x0000FF00);
337	addr = mfdcr(plb4_acr) \| 0xa0000000; /* Was 0x8---- */
338	mtdcr(plb4_acr, addr);
339
340	/*-------------------------------------------------------------------------+
341	\| Set Nebula PLB4 arbiter to fair mode.
342	+-------------------------------------------------------------------------*/
343	/* Segment0 */
344	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) \| plb0_acr_ppm_fair;
345	addr = (addr & ~plb0_acr_hbu_mask) \| plb0_acr_hbu_enabled;
346	addr = (addr & ~plb0_acr_rdp_mask) \| plb0_acr_rdp_4deep;
347	addr = (addr & ~plb0_acr_wrp_mask) \| plb0_acr_wrp_2deep;
348	mtdcr(plb0_acr, addr);
349
350	/* Segment1 */
351	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) \| plb1_acr_ppm_fair;
352	addr = (addr & ~plb1_acr_hbu_mask) \| plb1_acr_hbu_enabled;
353	addr = (addr & ~plb1_acr_rdp_mask) \| plb1_acr_rdp_4deep;
354	addr = (addr & ~plb1_acr_wrp_mask) \| plb1_acr_wrp_2deep;
355	mtdcr(plb1_acr, addr);
356
357	return 1;
358	}
359	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
360
361	/*************************************************************************
362	* pci_target_init
363	*
364	* The bootstrap configuration provides default settings for the pci
365	* inbound map (PIM). But the bootstrap config choices are limited and
366	* may not be sufficient for a given board.
367	*
368	************************************************************************/
369	#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
370	void pci_target_init(struct pci_controller *hose)
371	{
372	/*--------------------------------------------------------------------------+
373	* Set up Direct MMIO registers
374	--------------------------------------------------------------------------/
375	/*--------------------------------------------------------------------------+
376	\| PowerPC440 EP PCI Master configuration.
377	\| Map one 1Gig range of PLB/processor addresses to PCI memory space.
378	\| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
379	\| Use byte reversed out routines to handle endianess.
380	\| Make this region non-prefetchable.
381	+--------------------------------------------------------------------------*/
382	out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
383	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
384	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
385	out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
386	out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
387
388	out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
389	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
390	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
391	out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
392	out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
393
394	out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
395	out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
396	out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
397	out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
398
399	/*--------------------------------------------------------------------------+
400	* Set up Configuration registers
401	--------------------------------------------------------------------------/
402
403	/* Program the board's subsystem id/vendor id */
404	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
405	CFG_PCI_SUBSYS_VENDORID);
406	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
407
408	/* Configure command register as bus master */
409	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
410
411	/* 240nS PCI clock */
412	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
413
414	/* No error reporting */
415	pci_write_config_word(0, PCI_ERREN, 0);
416
417	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
418
419	}
420	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
421
422	/*************************************************************************
423	* pci_master_init
424	*
425	************************************************************************/
426	#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
427	void pci_master_init(struct pci_controller *hose)
428	{
429	unsigned short temp_short;
430
431	/*--------------------------------------------------------------------------+
432	\| Write the PowerPC440 EP PCI Configuration regs.
433	\| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
434	\| Enable PowerPC440 EP to act as a PCI memory target (PTM).
435	+--------------------------------------------------------------------------*/
436	pci_read_config_word(0, PCI_COMMAND, &temp_short);
437	pci_write_config_word(0, PCI_COMMAND,
438	temp_short \| PCI_COMMAND_MASTER \|
439	PCI_COMMAND_MEMORY);
440	}
441	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
442
443	/*************************************************************************
444	* is_pci_host
445	*
446	* This routine is called to determine if a pci scan should be
447	* performed. With various hardware environments (especially cPCI and
448	* PPMC) it's insufficient to depend on the state of the arbiter enable
449	* bit in the strap register, or generic host/adapter assumptions.
450	*
451	* Rather than hard-code a bad assumption in the general 440 code, the
452	* 440 pci code requires the board to decide at runtime.
453	*
454	* Return 0 for adapter mode, non-zero for host (monarch) mode.
455	*
456	*
457	************************************************************************/
458	#if defined(CONFIG_PCI)
459	int is_pci_host(struct pci_controller *hose)
460	{
461	/* Bamboo is always configured as host. */
462	return (1);
463	}
464	#endif /* defined(CONFIG_PCI) */
465
466	/*************************************************************************
467	* hw_watchdog_reset
468	*
469	* This routine is called to reset (keep alive) the watchdog timer
470	*
471	************************************************************************/
472	#if defined(CONFIG_HW_WATCHDOG)
473	void hw_watchdog_reset(void)
474	{
475
476	}
477	#endif