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Remove CONFIG_SYS_BOOTCOUNT_SINGLEWORD
[people/ms/u-boot.git] / board / aries / m53evk / m53evk.c
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0f83b365 1/*
2a4058c2 2 * Aries M53 module
0f83b365
MV		 3 *
4 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
0f83b365
MV		 7 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/imx-regs.h>
0f83b365
MV		 12#include <asm/arch/sys_proto.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/clock.h>
3fec2c67 15#include <asm/arch/iomux-mx53.h>
552a848e 16#include <asm/mach-imx/mx5_video.h>
9f2ec3f5 17#include <asm/spl.h>
1221ce45 18#include <linux/errno.h>
0f83b365
MV		 19#include <netdev.h>
20#include <i2c.h>
21#include <mmc.h>
22#include <spl.h>
23#include <fsl_esdhc.h>
24#include <asm/gpio.h>
e162c6b1 25#include <usb/ehci-ci.h>
502a710f
MV		 26#include <linux/fb.h>
27#include <ipu_pixfmt.h>
28
29/* Special MXCFB sync flags are here. */
30#include "../drivers/video/mxcfb.h"
0f83b365
MV		 31
32DECLARE_GLOBAL_DATA_PTR;
33
0f83b365
MV		 34static void setup_iomux_uart(void)
35{
3fec2c67
BT		 36 static const iomux_v3_cfg_t uart_pads[] = {
37 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
38 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
39 };
40
41 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
0f83b365
MV		 42}
43
44#ifdef CONFIG_USB_EHCI_MX5
45int board_ehci_hcd_init(int port)
46{
47 if (port == 0) {
48 /* USB OTG PWRON */
3fec2c67
BT		 49 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
50 PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
51 gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
0f83b365
MV		 52
53 /* USB OTG Over Current */
3fec2c67 54 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
0f83b365
MV		 55 } else if (port == 1) {
56 /* USB Host PWRON */
3fec2c67
BT		 57 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
58 PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
59 gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
0f83b365
MV		 60
61 /* USB Host Over Current */
3fec2c67 62 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
0f83b365
MV		 63 }
64
65 return 0;
66}
67#endif
68
69static void setup_iomux_fec(void)
70{
3fec2c67
BT		 71 static const iomux_v3_cfg_t fec_pads[] = {
72 /* MDIO pads */
73 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
74 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
75 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
76
77 /* FEC 0 pads */
78 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
79 PAD_CTL_HYS | PAD_CTL_PKE),
80 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
81 PAD_CTL_HYS | PAD_CTL_PKE),
82 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
83 PAD_CTL_HYS | PAD_CTL_PKE),
84 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
85 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
86 PAD_CTL_HYS | PAD_CTL_PKE),
87 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
88 PAD_CTL_HYS | PAD_CTL_PKE),
89 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
90 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
91
92 /* FEC 1 pads */
93 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
94 PAD_CTL_HYS | PAD_CTL_PKE),
95 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
96 PAD_CTL_HYS | PAD_CTL_PKE),
97 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
98 PAD_CTL_HYS | PAD_CTL_PKE),
99 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
100 PAD_CTL_HYS | PAD_CTL_PKE),
101 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
102 PAD_CTL_HYS | PAD_CTL_PKE),
103 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
104 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
105 PAD_CTL_HYS | PAD_CTL_PKE),
106 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
107 };
108
109 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
0f83b365
MV		 110}
111
112#ifdef CONFIG_FSL_ESDHC
113struct fsl_esdhc_cfg esdhc_cfg = {
114 MMC_SDHC1_BASE_ADDR,
115};
116
117int board_mmc_getcd(struct mmc *mmc)
118{
3fec2c67 119 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
0f83b365
MV		 120 gpio_direction_input(IMX_GPIO_NR(1, 1));
121
122 return !gpio_get_value(IMX_GPIO_NR(1, 1));
123}
124
3fec2c67
BT		 125#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
126 PAD_CTL_PUS_100K_UP)
127#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
128 PAD_CTL_DSE_HIGH)
129
0f83b365
MV		 130int board_mmc_init(bd_t *bis)
131{
3fec2c67
BT		 132 static const iomux_v3_cfg_t sd1_pads[] = {
133 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
134 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
135 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
136 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
137 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
138 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
139 MX53_PAD_EIM_DA13__GPIO3_13,
140
141 MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
142 };
143
0f83b365
MV		 144 esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
145
3fec2c67 146 imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
0f83b365
MV		 147
148 /* GPIO 2_31 is SD power */
0f83b365
MV		 149 gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
150
151 return fsl_esdhc_initialize(bis, &esdhc_cfg);
152}
153#endif
154
502a710f
MV		 155#ifdef CONFIG_VIDEO
156static struct fb_videomode const ampire_wvga = {
157 .name = "Ampire",
158 .refresh = 60,
159 .xres = 800,
160 .yres = 480,
161 .pixclock = 29851, /* picosecond (33.5 MHz) */
162 .left_margin = 89,
163 .right_margin = 164,
164 .upper_margin = 23,
165 .lower_margin = 10,
166 .hsync_len = 10,
167 .vsync_len = 10,
168 .sync = FB_SYNC_CLK_LAT_FALL,
169};
170
171int board_video_skip(void)
172{
173 int ret;
174 ret = ipuv3_fb_init(&ampire_wvga, 1, IPU_PIX_FMT_RGB666);
175 if (ret)
176 printf("Ampire LCD cannot be configured: %d\n", ret);
177 return ret;
178}
179#endif
180
3fec2c67
BT		 181#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
182 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
183
0f83b365
MV		 184static void setup_iomux_i2c(void)
185{
3fec2c67
BT		 186 static const iomux_v3_cfg_t i2c_pads[] = {
187 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
188 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
189 };
190
191 imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
0f83b365
MV		 192}
193
502a710f
MV		 194static void setup_iomux_video(void)
195{
196 static const iomux_v3_cfg_t lcd_pads[] = {
197 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
198 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
199 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
200 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
201 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
202 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
203 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
204 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
205 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
206 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
207 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
208 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
209 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
210 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
211 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
212 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
213 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
214 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
215 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
216 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
217 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
218 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
219 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
220 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
221 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
222 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
223 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
224 MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
225 MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
226 MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
227 MX53_PAD_EIM_A25__IPU_DI1_PIN12,
228 MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
229 };
230
231 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
232}
233
0f83b365
MV		 234static void setup_iomux_nand(void)
235{
3fec2c67
BT		 236 static const iomux_v3_cfg_t nand_pads[] = {
237 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
238 PAD_CTL_DSE_HIGH),
239 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
240 PAD_CTL_DSE_HIGH),
241 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
242 PAD_CTL_DSE_HIGH),
243 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
244 PAD_CTL_DSE_HIGH),
245 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
246 PAD_CTL_PUS_100K_UP),
247 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
248 PAD_CTL_PUS_100K_UP),
249 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
250 PAD_CTL_DSE_HIGH),
251 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
252 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
253 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
254 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
255 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
256 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
257 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
258 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
259 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
260 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
261 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
262 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
263 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
264 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
265 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
266 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
267 };
268
269 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
0f83b365
MV		 270}
271
272static void m53_set_clock(void)
273{
274 int ret;
275 const uint32_t ref_clk = MXC_HCLK;
276 const uint32_t dramclk = 400;
277 uint32_t cpuclk;
278
3fec2c67
BT		 279 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
280 PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
281 gpio_direction_input(IMX_GPIO_NR(4, 0));
0f83b365
MV		 282
283 /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
3fec2c67 284 cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
0f83b365
MV		 285
286 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
287 if (ret)
288 printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
289
290 ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
291 if (ret) {
292 printf("CPU: Switch peripheral clock to %dMHz failed\n",
293 dramclk);
294 }
295
296 ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
297 if (ret)
298 printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
299}
300
301static void m53_set_nand(void)
302{
303 u32 i;
304
305 /* NAND flash is muxed on ATA pins */
306 setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
307
308 /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
309 for (i = 0x4; i < 0x94; i += 0x18) {
310 clrbits_le32(WEIM_BASE_ADDR + i,
311 WEIM_GCR2_MUX16_BYP_GRANT_MASK);
312 }
313
314 mxc_set_clock(0, 33, MXC_NFC_CLK);
315 enable_nfc_clk(1);
316}
317
318int board_early_init_f(void)
319{
320 setup_iomux_uart();
321 setup_iomux_fec();
322 setup_iomux_i2c();
323 setup_iomux_nand();
502a710f 324 setup_iomux_video();
0f83b365
MV		 325
326 m53_set_clock();
327
328 mxc_set_sata_internal_clock();
329
330 /* NAND clock @ 33MHz */
331 m53_set_nand();
332
333 return 0;
334}
335
336int board_init(void)
337{
338 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
339
340 return 0;
341}
342
343int checkboard(void)
344{
2a4058c2 345 puts("Board: Aries M53EVK\n");
0f83b365
MV		 346
347 return 0;
348}
349
350/*
351 * NAND SPL
352 */
353#ifdef CONFIG_SPL_BUILD
354void spl_board_init(void)
355{
356 setup_iomux_nand();
357 m53_set_clock();
358 m53_set_nand();
359}
360
361u32 spl_boot_device(void)
362{
363 return BOOT_DEVICE_NAND;
364}
365#endif
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