]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/aries/ma5d4evk/ma5d4evk.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: at91: ma5d4: Enable DFU and UMS
[people/ms/u-boot.git] / board / aries / ma5d4evk / ma5d4evk.c
CommitLineData
c21c28b6
MV		 1/*
2 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/at91_common.h>
10#include <asm/arch/at91_pmc.h>
11#include <asm/arch/at91_rstc.h>
12#include <asm/arch/atmel_mpddrc.h>
13#include <asm/arch/atmel_usba_udc.h>
14#include <asm/arch/gpio.h>
15#include <asm/arch/clk.h>
16#include <asm/arch/sama5d3_smc.h>
17#include <asm/arch/sama5d4.h>
18#include <atmel_hlcdc.h>
19#include <atmel_mci.h>
20#include <lcd.h>
21#include <mmc.h>
22#include <net.h>
23#include <netdev.h>
24#include <spi.h>
25#include <version.h>
26
27DECLARE_GLOBAL_DATA_PTR;
28
29#ifdef CONFIG_ATMEL_SPI
30int spi_cs_is_valid(unsigned int bus, unsigned int cs)
31{
32 return bus == 0 && cs == 0;
33}
34
35void spi_cs_activate(struct spi_slave *slave)
36{
37 at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
38}
39
40void spi_cs_deactivate(struct spi_slave *slave)
41{
42 at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
43}
44
45static void ma5d4evk_spi0_hw_init(void)
46{
2dc63f73
WY		 47 at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
48 at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
49 at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
c21c28b6
MV		 50
51 at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
52
53 /* Enable clock */
54 at91_periph_clk_enable(ATMEL_ID_SPI0);
55}
56#endif /* CONFIG_ATMEL_SPI */
57
58#ifdef CONFIG_CMD_USB
59static void ma5d4evk_usb_hw_init(void)
60{
61 at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
62 at91_set_pio_output(AT91_PIO_PORTE, 14, 0);
63}
64#endif
65
66#ifdef CONFIG_LCD
67vidinfo_t panel_info = {
68 .vl_col = 800,
69 .vl_row = 480,
70 .vl_clk = 33500000,
71 .vl_bpix = LCD_BPP,
72 .vl_tft = 1,
73 .vl_hsync_len = 10,
74 .vl_left_margin = 89,
75 .vl_right_margin = 164,
76 .vl_vsync_len = 10,
77 .vl_upper_margin = 23,
78 .vl_lower_margin = 10,
79 .mmio = ATMEL_BASE_LCDC,
80};
81
82/* No power up/down pin for the LCD pannel */
83void lcd_enable(void) { /* Empty! */ }
84void lcd_disable(void) { /* Empty! */ }
85
86unsigned int has_lcdc(void)
87{
88 return 1;
89}
90
91static void ma5d4evk_lcd_hw_init(void)
92{
2dc63f73
WY		 93 at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 1); /* LCDPWM */
94 at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
95 at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
96 at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
97 at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
98 at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 1); /* LCDDEN */
99
100 at91_pio3_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
101 at91_pio3_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
102 at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
103 at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
104 at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
105 at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
106 at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
107 at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
108
109 at91_pio3_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
110 at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
111 at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
112 at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
113 at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
114 at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
115 at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
116 at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
117
118 at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
119 at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
120 at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
121 at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
122 at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
123 at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
124 at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
125 at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
c21c28b6
MV		 126
127 /* Enable clock */
128 at91_periph_clk_enable(ATMEL_ID_LCDC);
129}
130
131#endif /* CONFIG_LCD */
132
133#ifdef CONFIG_GENERIC_ATMEL_MCI
134/* On-SoM eMMC */
135void ma5d4evk_mci0_hw_init(void)
136{
2dc63f73
WY		 137 at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1); /* MCI1 CDA */
138 at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1); /* MCI1 DA0 */
139 at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1); /* MCI1 DA1 */
140 at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1); /* MCI1 DA2 */
141 at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1); /* MCI1 DA3 */
142 at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI1 DA4 */
143 at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI1 DA5 */
144 at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI1 DA6 */
145 at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI1 DA7 */
146 at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0); /* MCI1 CLK */
c21c28b6
MV		 147
148 /*
149 * As the mci io internal pull down is too strong, so if the io needs
150 * external pull up, the pull up resistor will be very small, if so
151 * the power consumption will increase, so disable the internal pull
152 * down to save the power.
153 */
2dc63f73
WY		 154 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
155 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
156 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
157 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
158 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
159 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
160 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
161 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
162 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
163 at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
c21c28b6
MV		 164
165 /* Enable clock */
166 at91_periph_clk_enable(ATMEL_ID_MCI0);
167}
168
169/* On-board MicroSD slot */
170void ma5d4evk_mci1_hw_init(void)
171{
2dc63f73
WY		 172 at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
173 at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
174 at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
175 at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
176 at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
177 at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
c21c28b6
MV		 178
179 /*
180 * As the mci io internal pull down is too strong, so if the io needs
181 * external pull up, the pull up resistor will be very small, if so
182 * the power consumption will increase, so disable the internal pull
183 * down to save the power.
184 */
2dc63f73
WY		 185 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
186 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
187 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
188 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
189 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
190 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
c21c28b6
MV		 191
192 /* Deal with WP pin on the microSD slot. */
193 at91_set_pio_output(AT91_PIO_PORTE, 16, 0);
2dc63f73 194 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
c21c28b6
MV		 195
196 /* Enable clock */
197 at91_periph_clk_enable(ATMEL_ID_MCI1);
198}
199
200int board_mmc_init(bd_t *bis)
201{
202 int ret;
203
204 /* De-assert reset on On-SoM eMMC */
205 at91_set_pio_output(AT91_PIO_PORTE, 15, 1);
2dc63f73 206 at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
c21c28b6
MV		 207
208 ret = atmel_mci_init((void *)ATMEL_BASE_MCI0);
209 if (ret) /* eMMC init failed, skip it. */
210 at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
211
212 /* Enable the power supply to On-board MicroSD */
213 at91_set_pio_output(AT91_PIO_PORTE, 17, 0);
214
215 ret = atmel_mci_init((void *)ATMEL_BASE_MCI1);
216 if (ret) /* uSD init failed, power it down. */
217 at91_set_pio_output(AT91_PIO_PORTE, 17, 1);
218
219 return 0;
220}
221#endif /* CONFIG_GENERIC_ATMEL_MCI */
222
223#ifdef CONFIG_MACB
224void ma5d4evk_macb0_hw_init(void)
225{
2dc63f73
WY		 226 at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
227 at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
228 at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
229 at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
230 at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
231 at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
232 at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
233 at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
234 at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
235 at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
c21c28b6
MV		 236
237 /* Enable clock */
238 at91_periph_clk_enable(ATMEL_ID_GMAC0);
239}
240#endif
241
242static void ma5d4evk_serial_hw_init(void)
243{
244 /* USART0 */
2dc63f73
WY		 245 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD */
246 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD */
247 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS */
248 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0); /* CTS */
c21c28b6
MV		 249 at91_periph_clk_enable(ATMEL_ID_USART0);
250
251 /* USART1 */
2dc63f73
WY		 252 at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD */
253 at91_pio3_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD */
254 at91_pio3_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS */
255 at91_pio3_set_a_periph(AT91_PIO_PORTD, 14, 0); /* CTS */
c21c28b6
MV		 256 at91_periph_clk_enable(ATMEL_ID_USART1);
257}
258
259int board_early_init_f(void)
260{
261 at91_periph_clk_enable(ATMEL_ID_PIOA);
262 at91_periph_clk_enable(ATMEL_ID_PIOB);
263 at91_periph_clk_enable(ATMEL_ID_PIOC);
264 at91_periph_clk_enable(ATMEL_ID_PIOD);
265 at91_periph_clk_enable(ATMEL_ID_PIOE);
266
267 /* Configure LEDs as OFF */
268 at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
269 at91_set_pio_output(AT91_PIO_PORTD, 29, 0);
270 at91_set_pio_output(AT91_PIO_PORTD, 30, 0);
271
c21c28b6
MV		 272 ma5d4evk_serial_hw_init();
273
274 return 0;
275}
276
277int board_init(void)
278{
279 /* adress of boot parameters */
280 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
281
282#ifdef CONFIG_ATMEL_SPI
283 ma5d4evk_spi0_hw_init();
284#endif
285#ifdef CONFIG_GENERIC_ATMEL_MCI
286 ma5d4evk_mci0_hw_init();
287 ma5d4evk_mci1_hw_init();
288#endif
289#ifdef CONFIG_MACB
290 ma5d4evk_macb0_hw_init();
291#endif
292#ifdef CONFIG_LCD
293 ma5d4evk_lcd_hw_init();
294#endif
295#ifdef CONFIG_CMD_USB
296 ma5d4evk_usb_hw_init();
297#endif
298#ifdef CONFIG_USB_GADGET_ATMEL_USBA
299 at91_udp_hw_init();
300#endif
301
52a557d6
MV		 302 /* Reset CAN controllers */
303 at91_set_pio_output(AT91_PIO_PORTB, 21, 0);
304 udelay(100);
305 at91_set_pio_output(AT91_PIO_PORTB, 21, 1);
306 at91_pio3_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
307
c21c28b6
MV		 308 return 0;
309}
310
311int dram_init(void)
312{
313 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
314 CONFIG_SYS_SDRAM_SIZE);
315 return 0;
316}
317
318int board_eth_init(bd_t *bis)
319{
320 int rc = 0;
321
322#ifdef CONFIG_MACB
323 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
324#endif
325
326#ifdef CONFIG_USB_GADGET_ATMEL_USBA
327 usba_udc_probe(&pdata);
328#ifdef CONFIG_USB_ETH_RNDIS
329 usb_eth_initialize(bis);
330#endif
331#endif
332
333 return rc;
334}
335
336/* SPL */
337#ifdef CONFIG_SPL_BUILD
338void spl_board_init(void)
339{
340 ma5d4evk_spi0_hw_init();
341}
342
343static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
344{
345 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
346
347 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
348 ATMEL_MPDDRC_CR_NR_ROW_13 |
349 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
350 ATMEL_MPDDRC_CR_NB_8BANKS |
351 ATMEL_MPDDRC_CR_NDQS_DISABLED |
c21c28b6
MV		 352 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
353
354 ddr2->rtr = 0x2b0;
355
356 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
357 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
358 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
359 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
360 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
361 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
362 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
363 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
364
365 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
366 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
367 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
368 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
369
370 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
371 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
372 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
373 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
374 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
375}
376
377void mem_init(void)
378{
379 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
380 struct atmel_mpddrc_config ddr2;
381
382 ddr2_conf(&ddr2);
383
384 /* enable MPDDR clock */
385 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
386 writel(AT91_PMC_DDR, &pmc->scer);
387
388 /* DDRAM2 Controller initialize */
389 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
390}
391
392void at91_pmc_init(void)
393{
394 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
395 u32 tmp;
396
397 tmp = AT91_PMC_PLLAR_29 |
398 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
399 AT91_PMC_PLLXR_MUL(87) |
400 AT91_PMC_PLLXR_DIV(1);
401 at91_plla_init(tmp);
402
403 writel(0x0 << 8, &pmc->pllicpr);
404
405 tmp = AT91_PMC_MCKR_H32MXDIV |
406 AT91_PMC_MCKR_PLLADIV_2 |
407 AT91_PMC_MCKR_MDIV_3 |
408 AT91_PMC_MCKR_CSS_PLLA;
409 at91_mck_init(tmp);
410}
411#endif
"Das U-Boot" Source Tree