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e379c039 HS |
1 | /* |
2 | * (C) Copyright 2014 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
5 | * Based on: | |
6 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
7 | * | |
8 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0+ | |
11 | */ | |
12 | ||
13 | #include <asm/arch/clock.h> | |
14 | #include <asm/arch/imx-regs.h> | |
15 | #include <asm/arch/iomux.h> | |
16 | #include <asm/arch/mx6-pins.h> | |
17 | #include <asm/errno.h> | |
18 | #include <asm/gpio.h> | |
19 | #include <asm/imx-common/iomux-v3.h> | |
20 | #include <asm/imx-common/boot_mode.h> | |
21 | #include <asm/imx-common/mxc_i2c.h> | |
22 | #include <asm/imx-common/video.h> | |
23 | #include <mmc.h> | |
24 | #include <fsl_esdhc.h> | |
25 | #include <miiphy.h> | |
26 | #include <netdev.h> | |
27 | #include <asm/arch/mxc_hdmi.h> | |
28 | #include <asm/arch/crm_regs.h> | |
29 | #include <linux/fb.h> | |
30 | #include <ipu_pixfmt.h> | |
31 | #include <asm/io.h> | |
32 | #include <asm/arch/sys_proto.h> | |
33 | #include <pwm.h> | |
34 | ||
35 | DECLARE_GLOBAL_DATA_PTR; | |
36 | ||
37 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | |
38 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ | |
39 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
40 | ||
41 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ | |
42 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ | |
43 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
44 | ||
45 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | |
46 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | |
47 | ||
48 | #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ | |
49 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) | |
50 | ||
51 | #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | |
52 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ | |
53 | PAD_CTL_ODE | PAD_CTL_SRE_FAST) | |
54 | ||
55 | #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) | |
56 | ||
57 | #define DISP_PAD_CTRL (0x10) | |
58 | ||
59 | #define ECSPI4_CS1 IMX_GPIO_NR(5, 2) | |
60 | ||
61 | struct i2c_pads_info i2c_pad_info1 = { | |
62 | .scl = { | |
63 | .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, | |
64 | .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, | |
65 | .gp = IMX_GPIO_NR(5, 27) | |
66 | }, | |
67 | .sda = { | |
68 | .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, | |
69 | .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, | |
70 | .gp = IMX_GPIO_NR(5, 26) | |
71 | } | |
72 | }; | |
73 | ||
74 | struct i2c_pads_info i2c_pad_info2 = { | |
75 | .scl = { | |
76 | .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, | |
77 | .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, | |
78 | .gp = IMX_GPIO_NR(4, 12) | |
79 | }, | |
80 | .sda = { | |
81 | .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, | |
82 | .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, | |
83 | .gp = IMX_GPIO_NR(4, 13) | |
84 | } | |
85 | }; | |
86 | ||
87 | struct i2c_pads_info i2c_pad_info3 = { | |
88 | .scl = { | |
89 | .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, | |
90 | .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, | |
91 | .gp = IMX_GPIO_NR(3, 17) | |
92 | }, | |
93 | .sda = { | |
94 | .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, | |
95 | .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, | |
96 | .gp = IMX_GPIO_NR(3, 18) | |
97 | } | |
98 | }; | |
99 | ||
100 | int dram_init(void) | |
101 | { | |
102 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
107 | iomux_v3_cfg_t const uart1_pads[] = { | |
108 | MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
109 | MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
110 | }; | |
111 | ||
112 | iomux_v3_cfg_t const uart5_pads[] = { | |
113 | MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
114 | MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
115 | }; | |
116 | ||
117 | iomux_v3_cfg_t const gpio_pads[] = { | |
118 | /* LED enable */ | |
119 | MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
120 | /* spi flash WP protect */ | |
121 | MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
122 | /* backlight enable */ | |
123 | MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
124 | /* LED yellow */ | |
125 | MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
126 | /* LED red */ | |
127 | MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
128 | /* LED green */ | |
129 | MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
130 | /* LED blue */ | |
131 | MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
132 | /* i2c4 scl */ | |
133 | MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
134 | /* i2c4 sda */ | |
135 | MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
136 | /* spi CS 1 */ | |
137 | MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
138 | }; | |
139 | ||
140 | static iomux_v3_cfg_t const misc_pads[] = { | |
141 | MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), | |
142 | /* OTG Power enable */ | |
143 | MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
144 | MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
145 | }; | |
146 | ||
147 | iomux_v3_cfg_t const enet_pads[] = { | |
148 | MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8), | |
149 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
150 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
151 | MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
152 | MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
153 | MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
154 | MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
155 | MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
156 | MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
157 | MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
158 | }; | |
159 | ||
160 | static void setup_iomux_enet(void) | |
161 | { | |
162 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
163 | ||
164 | imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); | |
165 | ||
166 | /* set GPIO_16 as ENET_REF_CLK_OUT */ | |
167 | setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); | |
168 | } | |
169 | ||
170 | iomux_v3_cfg_t const usdhc1_pads[] = { | |
171 | MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
172 | MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
173 | MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
174 | MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
175 | MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
176 | MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
177 | }; | |
178 | ||
179 | iomux_v3_cfg_t const usdhc2_pads[] = { | |
180 | MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
181 | MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
182 | MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
183 | MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
184 | MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
185 | MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
186 | }; | |
187 | ||
188 | iomux_v3_cfg_t const ecspi4_pads[] = { | |
189 | MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL), | |
190 | MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL), | |
191 | MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL), | |
192 | MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
193 | }; | |
194 | ||
195 | static iomux_v3_cfg_t const display_pads[] = { | |
196 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), | |
197 | MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, | |
198 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, | |
199 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, | |
200 | MX6_PAD_DI0_PIN4__GPIO4_IO20, | |
201 | MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, | |
202 | MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, | |
203 | MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, | |
204 | MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, | |
205 | MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, | |
206 | MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, | |
207 | MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, | |
208 | MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, | |
209 | MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, | |
210 | MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, | |
211 | MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, | |
212 | MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, | |
213 | MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, | |
214 | MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, | |
215 | MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, | |
216 | MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, | |
217 | MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, | |
218 | MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, | |
219 | MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, | |
220 | MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, | |
221 | MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, | |
222 | MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, | |
223 | MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, | |
224 | MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, | |
225 | }; | |
226 | ||
227 | static iomux_v3_cfg_t const backlight_pads[] = { | |
228 | MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), | |
229 | MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), | |
230 | MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
231 | }; | |
232 | ||
233 | static void setup_spi(void) | |
234 | { | |
235 | int i; | |
236 | ||
237 | imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); | |
238 | for (i = 0; i < 3; i++) | |
239 | enable_spi_clk(true, i); | |
240 | ||
241 | /* set cs1 to high */ | |
242 | gpio_direction_output(ECSPI4_CS1, 1); | |
243 | } | |
244 | ||
245 | static void setup_iomux_gpio(void) | |
246 | { | |
247 | imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); | |
248 | } | |
249 | ||
250 | static void setup_iomux_uart(void) | |
251 | { | |
252 | imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); | |
253 | } | |
254 | ||
255 | #ifdef CONFIG_FSL_ESDHC | |
256 | struct fsl_esdhc_cfg usdhc_cfg[2] = { | |
257 | {USDHC1_BASE_ADDR}, | |
258 | {USDHC2_BASE_ADDR}, | |
259 | }; | |
260 | ||
261 | int board_mmc_getcd(struct mmc *mmc) | |
262 | { | |
263 | return 1; | |
264 | } | |
265 | ||
266 | int board_mmc_init(bd_t *bis) | |
267 | { | |
268 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); | |
269 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); | |
270 | ||
271 | imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); | |
272 | imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); | |
273 | ||
274 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) | | |
275 | fsl_esdhc_initialize(bis, &usdhc_cfg[1]); | |
276 | } | |
277 | #endif | |
278 | ||
279 | /* | |
280 | * Do not overwrite the console | |
281 | * Use always serial for U-Boot console | |
282 | */ | |
283 | int overwrite_console(void) | |
284 | { | |
285 | return 1; | |
286 | } | |
287 | ||
288 | int board_eth_init(bd_t *bis) | |
289 | { | |
290 | struct iomuxc *iomuxc_regs = | |
291 | (struct iomuxc *)IOMUXC_BASE_ADDR; | |
292 | int ret; | |
293 | ||
294 | setup_iomux_enet(); | |
295 | /* clear gpr1[14], gpr1[18:17] to select anatop clock */ | |
296 | clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); | |
297 | ||
298 | ret = enable_fec_anatop_clock(ENET_50MHz); | |
299 | if (ret) | |
300 | return ret; | |
301 | ||
302 | return cpu_eth_init(bis); | |
303 | } | |
304 | #if defined(CONFIG_VIDEO_IPUV3) | |
305 | ||
306 | static void enable_lvds(struct display_info_t const *dev) | |
307 | { | |
308 | imx_iomux_v3_setup_multiple_pads( | |
309 | display_pads, | |
310 | ARRAY_SIZE(display_pads)); | |
311 | imx_iomux_v3_setup_multiple_pads( | |
312 | backlight_pads, | |
313 | ARRAY_SIZE(backlight_pads)); | |
314 | ||
315 | /* enable backlight PWM 3 */ | |
316 | if (pwm_init(2, 0, 0)) | |
317 | goto error; | |
318 | /* duty cycle 200ns, period: 3000ns */ | |
319 | if (pwm_config(2, 200, 3000)) | |
320 | goto error; | |
321 | if (pwm_enable(2)) | |
322 | goto error; | |
323 | return; | |
324 | ||
325 | error: | |
326 | puts("error init pwm for backlight\n"); | |
327 | return; | |
328 | } | |
329 | ||
330 | struct display_info_t const displays[] = { | |
331 | { | |
332 | .bus = -1, | |
333 | .addr = 0, | |
334 | .pixfmt = IPU_PIX_FMT_RGB24, | |
335 | .detect = NULL, | |
336 | .enable = enable_lvds, | |
337 | .mode = { | |
338 | .name = "lb07wv8", | |
339 | .refresh = 60, | |
340 | .xres = 800, | |
341 | .yres = 480, | |
342 | .pixclock = 33246, | |
343 | .left_margin = 88, | |
344 | .right_margin = 88, | |
345 | .upper_margin = 10, | |
346 | .lower_margin = 10, | |
347 | .hsync_len = 25, | |
348 | .vsync_len = 1, | |
349 | .sync = 0, | |
350 | .vmode = FB_VMODE_NONINTERLACED | |
351 | } | |
352 | } | |
353 | }; | |
354 | size_t display_count = ARRAY_SIZE(displays); | |
355 | ||
356 | static void setup_display(void) | |
357 | { | |
358 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
359 | int reg; | |
360 | ||
361 | enable_ipu_clock(); | |
362 | ||
363 | reg = readl(&mxc_ccm->cs2cdr); | |
364 | /* select pll 5 clock */ | |
365 | reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK; | |
366 | reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK; | |
367 | writel(reg, &mxc_ccm->cs2cdr); | |
368 | ||
369 | imx_iomux_v3_setup_multiple_pads(backlight_pads, | |
370 | ARRAY_SIZE(backlight_pads)); | |
371 | } | |
372 | ||
373 | /* no console on this board */ | |
374 | int board_cfb_skip(void) | |
375 | { | |
376 | return 1; | |
377 | } | |
378 | #endif | |
379 | ||
380 | int board_early_init_f(void) | |
381 | { | |
382 | setup_iomux_uart(); | |
383 | setup_iomux_gpio(); | |
384 | ||
385 | #if defined(CONFIG_VIDEO_IPUV3) | |
386 | setup_display(); | |
387 | #endif | |
388 | return 0; | |
389 | } | |
390 | ||
391 | iomux_v3_cfg_t nfc_pads[] = { | |
392 | MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), | |
393 | MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), | |
394 | MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), | |
395 | MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), | |
396 | MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), | |
397 | MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), | |
398 | MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), | |
399 | MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), | |
400 | MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), | |
401 | MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), | |
402 | MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
403 | MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
404 | MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
405 | MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
406 | MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
407 | MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
408 | MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
409 | MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
410 | MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), | |
411 | }; | |
412 | ||
413 | static void setup_gpmi_nand(void) | |
414 | { | |
415 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
416 | ||
417 | /* config gpmi nand iomux */ | |
418 | imx_iomux_v3_setup_multiple_pads(nfc_pads, | |
419 | ARRAY_SIZE(nfc_pads)); | |
420 | ||
421 | /* config gpmi and bch clock to 100 MHz */ | |
422 | clrsetbits_le32(&mxc_ccm->cs2cdr, | |
423 | MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | | |
424 | MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | | |
425 | MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, | |
426 | MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | | |
427 | MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | | |
428 | MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); | |
429 | ||
430 | /* enable gpmi and bch clock gating */ | |
431 | setbits_le32(&mxc_ccm->CCGR4, | |
432 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
433 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
434 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
435 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
436 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); | |
437 | ||
438 | /* enable apbh clock gating */ | |
439 | setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); | |
440 | } | |
441 | ||
442 | int board_init(void) | |
443 | { | |
444 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
445 | ||
446 | /* address of boot parameters */ | |
447 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
448 | ||
449 | setup_spi(); | |
450 | ||
451 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, | |
452 | &i2c_pad_info1); | |
453 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, | |
454 | &i2c_pad_info2); | |
455 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, | |
456 | &i2c_pad_info3); | |
457 | ||
458 | /* i2c4 not used, set it to gpio input */ | |
459 | gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl"); | |
460 | gpio_direction_input(IMX_GPIO_NR(1, 7)); | |
461 | gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda"); | |
462 | gpio_direction_input(IMX_GPIO_NR(1, 8)); | |
463 | ||
464 | /* SPI NOR Flash read only */ | |
465 | gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor"); | |
466 | gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0); | |
467 | gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH); | |
468 | ||
469 | /* enable LED */ | |
470 | gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); | |
471 | gpio_direction_output(IMX_GPIO_NR(2, 13), 0); | |
472 | ||
473 | gpio_request(IMX_GPIO_NR(1, 3), "LED yellow"); | |
474 | gpio_direction_output(IMX_GPIO_NR(1, 3), 1); | |
475 | gpio_request(IMX_GPIO_NR(1, 4), "LED red"); | |
476 | gpio_direction_output(IMX_GPIO_NR(1, 4), 1); | |
477 | gpio_request(IMX_GPIO_NR(1, 5), "LED green"); | |
478 | gpio_direction_output(IMX_GPIO_NR(1, 5), 1); | |
479 | gpio_request(IMX_GPIO_NR(1, 6), "LED blue"); | |
480 | gpio_direction_output(IMX_GPIO_NR(1, 6), 1); | |
481 | ||
482 | setup_gpmi_nand(); | |
483 | ||
484 | /* GPIO_1 for USB_OTG_ID */ | |
485 | setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK); | |
486 | imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); | |
487 | ||
488 | return 0; | |
489 | } | |
490 | ||
491 | int checkboard(void) | |
492 | { | |
493 | puts("Board: aristaitenos\n"); | |
494 | return 0; | |
495 | } | |
496 | ||
497 | #ifdef CONFIG_USB_EHCI_MX6 | |
498 | int board_ehci_hcd_init(int port) | |
499 | { | |
500 | int ret; | |
501 | ||
502 | ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr"); | |
503 | if (!ret) | |
504 | gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1); | |
505 | ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr"); | |
506 | if (!ret) | |
507 | gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1); | |
508 | return 0; | |
509 | } | |
510 | ||
511 | int board_ehci_power(int port, int on) | |
512 | { | |
513 | if (port) | |
514 | gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on); | |
515 | else | |
516 | gpio_set_value(ARISTAINETOS_USB_H1_PWR, on); | |
517 | return 0; | |
518 | } | |
519 | #endif |