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bcc05c7a | 1 | /* |
2 | * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __APF27_H | |
8 | #define __APF27_H | |
9 | ||
10 | /* FPGA program pin configuration */ | |
11 | #define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */ | |
12 | #define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */ | |
13 | #define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */ | |
14 | #define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */ | |
15 | #define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */ | |
16 | #define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */ | |
17 | #define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */ | |
18 | #define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */ | |
19 | #define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */ | |
20 | #define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */ | |
21 | #define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */ | |
22 | ||
23 | /* MMC pin */ | |
24 | #define PC_PWRON (GPIO_PORTF | 16) | |
25 | ||
26 | /* | |
27 | * MPU CLOCK source before PLL | |
28 | * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) | |
29 | */ | |
30 | #define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */ | |
31 | #define ACFG_MPCTL1_VAL 0 | |
32 | #define CONFIG_MPLL_FREQ 399 | |
33 | ||
34 | #define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */ | |
35 | ||
36 | /* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/ | |
37 | #define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */ | |
38 | #define ACFG_SPCTL1_VAL 0 | |
39 | #define CONFIG_SPLL_FREQ 300 /* MHz */ | |
40 | ||
41 | /* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */ | |
42 | #define CONFIG_ARM_FREQ 399 /* up to 400 MHz */ | |
43 | ||
44 | /* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */ | |
45 | #define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */ | |
46 | ||
47 | #define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */ | |
48 | #define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */ | |
49 | #define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */ | |
50 | #define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */ | |
51 | #define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */ | |
52 | #define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */ | |
53 | #define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */ | |
54 | #define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */ | |
55 | #define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */ | |
56 | #define CONFIG_CLK0_EN 1 /* CLK0 enabled */ | |
57 | ||
58 | /* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */ | |
59 | #define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */ | |
60 | ||
61 | /* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */ | |
62 | #define CONFIG_USB_FREQ 60 /* 60 MHz */ | |
63 | ||
64 | /* | |
65 | * SDRAM | |
66 | */ | |
67 | #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ | |
68 | /* micron 64MB */ | |
69 | #define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 | |
70 | * column address bits | |
71 | */ | |
72 | #define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13 | |
73 | * row address bits | |
74 | */ | |
75 | #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 | |
76 | * 2=4096 3=8192 refresh | |
77 | */ | |
78 | #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power | |
79 | * down delay | |
80 | */ | |
81 | #define ACFG_SDRAM_W2R_DELAY 1 /* write to read | |
82 | * cycle delay > 0 | |
83 | */ | |
84 | #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ | |
85 | #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register | |
86 | * cycle delay 1..4 | |
87 | */ | |
88 | #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck | |
89 | * SDRAM: 0=1ck 1=2ck | |
90 | */ | |
91 | #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ | |
92 | #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ | |
93 | #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ | |
94 | #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC | |
95 | * refresh to command) | |
96 | */ | |
97 | #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time | |
98 | * estimated fo CL=1 | |
99 | * 0=force 3 for lpddr | |
100 | */ | |
101 | #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater | |
102 | * 3=Eighth 4=Sixteenth | |
103 | */ | |
104 | #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half | |
105 | * 2=quater 3=Eighth | |
106 | */ | |
107 | #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ | |
108 | #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access | |
109 | * 0 = Burst mode | |
110 | */ | |
111 | #endif | |
112 | ||
113 | #if (ACFG_SDRAM_MBYTE_SYZE == 128) | |
114 | /* micron 128MB */ | |
115 | #define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 | |
116 | * column address bits | |
117 | */ | |
118 | #define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 | |
119 | * row address bits | |
120 | */ | |
121 | #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 | |
122 | * 2=4096 3=8192 refresh | |
123 | */ | |
124 | #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power | |
125 | * down delay | |
126 | */ | |
127 | #define ACFG_SDRAM_W2R_DELAY 1 /* write to read | |
128 | * cycle delay > 0 | |
129 | */ | |
130 | #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ | |
131 | #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register | |
132 | * cycle delay 1..4 | |
133 | */ | |
134 | #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck | |
135 | * SDRAM: 0=1ck 1=2ck | |
136 | */ | |
137 | #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ | |
138 | #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ | |
139 | #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ | |
140 | #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC | |
141 | * refresh to command) | |
142 | */ | |
143 | #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time | |
144 | * estimated fo CL=1 | |
145 | * 0=force 3 for lpddr | |
146 | */ | |
147 | #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater | |
148 | * 3=Eighth 4=Sixteenth | |
149 | */ | |
150 | #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half | |
151 | * 2=quater 3=Eighth | |
152 | */ | |
153 | #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ | |
154 | #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access | |
155 | * 0 = Burst mode | |
156 | */ | |
157 | #endif | |
158 | ||
159 | #if (ACFG_SDRAM_MBYTE_SYZE == 256) | |
160 | /* micron 256MB */ | |
161 | #define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 | |
162 | * column address bits | |
163 | */ | |
164 | #define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 | |
165 | * row address bits | |
166 | */ | |
167 | #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 | |
168 | * 2=4096 3=8192 refresh | |
169 | */ | |
170 | #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power | |
171 | * down delay | |
172 | */ | |
173 | #define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle | |
174 | * delay > 0 | |
175 | */ | |
176 | #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ | |
177 | #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register | |
178 | * cycle delay 1..4 | |
179 | */ | |
180 | #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck | |
181 | * SDRAM: 0=1ck 1=2ck | |
182 | */ | |
183 | #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ | |
184 | #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ | |
185 | #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ | |
186 | #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC | |
187 | * refresh to command) | |
188 | */ | |
189 | #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time | |
190 | * estimated fo CL=1 | |
191 | * 0=force 3 for lpddr | |
192 | */ | |
193 | #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater | |
194 | * 3=Eighth 4=Sixteenth | |
195 | */ | |
196 | #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength | |
197 | * 1=half | |
198 | * 2=quater | |
199 | * 3=Eighth | |
200 | */ | |
201 | #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ | |
202 | #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access | |
203 | * 0 = Burst mode | |
204 | */ | |
205 | #endif | |
206 | ||
207 | /* | |
208 | * External interface | |
209 | */ | |
210 | /* | |
211 | * CSCRxU_VAL: | |
212 | * 31| x | x | x x |x x x x| x x | x | x |x x x x|16 | |
213 | * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL | | |
214 | * | |
215 | * 15| x x | x x x x x x | x | x x x x | x x x x |0 | |
216 | * | CNC | WSC |EW | WWS | EDC | | |
217 | * | |
218 | * CSCRxL_VAL: | |
219 | * 31| x x x x | x x x x | x x x x | x x x x |16 | |
220 | * | OEA | OEN | EBWA | EBWN | | |
221 | * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0 | |
222 | * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN| | |
223 | * | |
224 | * CSCRxA_VAL: | |
225 | * 31| x x x x | x x x x | x x x x | x x x x |16 | |
226 | * | EBRA | EBRN | RWA | RWN | | |
227 | * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0 | |
228 | * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE| | |
229 | */ | |
230 | ||
231 | /* CS0 configuration for 16 bit nor flash */ | |
232 | #define ACFG_CS0U_VAL 0x0000CC03 | |
233 | #define ACFG_CS0L_VAL 0xa0330D01 | |
234 | #define ACFG_CS0A_VAL 0x00220800 | |
235 | ||
236 | #define ACFG_CS1U_VAL 0x00000f00 | |
237 | #define ACFG_CS1L_VAL 0x00000D01 | |
238 | #define ACFG_CS1A_VAL 0 | |
239 | ||
240 | #define ACFG_CS2U_VAL 0 | |
241 | #define ACFG_CS2L_VAL 0 | |
242 | #define ACFG_CS2A_VAL 0 | |
243 | ||
244 | #define ACFG_CS3U_VAL 0 | |
245 | #define ACFG_CS3L_VAL 0 | |
246 | #define ACFG_CS3A_VAL 0 | |
247 | ||
248 | #define ACFG_CS4U_VAL 0 | |
249 | #define ACFG_CS4L_VAL 0 | |
250 | #define ACFG_CS4A_VAL 0 | |
251 | ||
252 | /* FPGA 16 bit data bus */ | |
253 | #define ACFG_CS5U_VAL 0x00000600 | |
254 | #define ACFG_CS5L_VAL 0x00000D01 | |
255 | #define ACFG_CS5A_VAL 0 | |
256 | ||
257 | #define ACFG_EIM_VAL 0x00002200 | |
258 | ||
259 | ||
260 | /* | |
261 | * FPGA specific settings | |
262 | */ | |
263 | ||
264 | /* CLKO */ | |
265 | #define ACFG_CCSR_VAL 0x00000305 | |
266 | /* drive strength CLKO set to 2 */ | |
267 | #define ACFG_DSCR10_VAL 0x00020000 | |
268 | /* drive strength A1..A12 set to 2 */ | |
269 | #define ACFG_DSCR3_VAL 0x02AAAAA8 | |
270 | /* drive strength ctrl */ | |
271 | #define ACFG_DSCR7_VAL 0x00020880 | |
272 | /* drive strength data */ | |
273 | #define ACFG_DSCR2_VAL 0xAAAAAAAA | |
274 | ||
275 | ||
276 | /* | |
277 | * Default configuration for GPIOs and peripherals | |
278 | */ | |
279 | #define ACFG_DDIR_A_VAL 0x00000000 | |
280 | #define ACFG_OCR1_A_VAL 0x00000000 | |
281 | #define ACFG_OCR2_A_VAL 0x00000000 | |
282 | #define ACFG_ICFA1_A_VAL 0xFFFFFFFF | |
283 | #define ACFG_ICFA2_A_VAL 0xFFFFFFFF | |
284 | #define ACFG_ICFB1_A_VAL 0xFFFFFFFF | |
285 | #define ACFG_ICFB2_A_VAL 0xFFFFFFFF | |
286 | #define ACFG_DR_A_VAL 0x00000000 | |
287 | #define ACFG_GIUS_A_VAL 0xFFFFFFFF | |
288 | #define ACFG_ICR1_A_VAL 0x00000000 | |
289 | #define ACFG_ICR2_A_VAL 0x00000000 | |
290 | #define ACFG_IMR_A_VAL 0x00000000 | |
291 | #define ACFG_GPR_A_VAL 0x00000000 | |
292 | #define ACFG_PUEN_A_VAL 0xFFFFFFFF | |
293 | ||
294 | #define ACFG_DDIR_B_VAL 0x00000000 | |
295 | #define ACFG_OCR1_B_VAL 0x00000000 | |
296 | #define ACFG_OCR2_B_VAL 0x00000000 | |
297 | #define ACFG_ICFA1_B_VAL 0xFFFFFFFF | |
298 | #define ACFG_ICFA2_B_VAL 0xFFFFFFFF | |
299 | #define ACFG_ICFB1_B_VAL 0xFFFFFFFF | |
300 | #define ACFG_ICFB2_B_VAL 0xFFFFFFFF | |
301 | #define ACFG_DR_B_VAL 0x00000000 | |
302 | #define ACFG_GIUS_B_VAL 0xFF3FFFF0 | |
303 | #define ACFG_ICR1_B_VAL 0x00000000 | |
304 | #define ACFG_ICR2_B_VAL 0x00000000 | |
305 | #define ACFG_IMR_B_VAL 0x00000000 | |
306 | #define ACFG_GPR_B_VAL 0x00000000 | |
307 | #define ACFG_PUEN_B_VAL 0xFFFFFFFF | |
308 | ||
309 | #define ACFG_DDIR_C_VAL 0x00000000 | |
310 | #define ACFG_OCR1_C_VAL 0x00000000 | |
311 | #define ACFG_OCR2_C_VAL 0x00000000 | |
312 | #define ACFG_ICFA1_C_VAL 0xFFFFFFFF | |
313 | #define ACFG_ICFA2_C_VAL 0xFFFFFFFF | |
314 | #define ACFG_ICFB1_C_VAL 0xFFFFFFFF | |
315 | #define ACFG_ICFB2_C_VAL 0xFFFFFFFF | |
316 | #define ACFG_DR_C_VAL 0x00000000 | |
317 | #define ACFG_GIUS_C_VAL 0xFFFFC07F | |
318 | #define ACFG_ICR1_C_VAL 0x00000000 | |
319 | #define ACFG_ICR2_C_VAL 0x00000000 | |
320 | #define ACFG_IMR_C_VAL 0x00000000 | |
321 | #define ACFG_GPR_C_VAL 0x00000000 | |
322 | #define ACFG_PUEN_C_VAL 0xFFFFFF87 | |
323 | ||
324 | #define ACFG_DDIR_D_VAL 0x00000000 | |
325 | #define ACFG_OCR1_D_VAL 0x00000000 | |
326 | #define ACFG_OCR2_D_VAL 0x00000000 | |
327 | #define ACFG_ICFA1_D_VAL 0xFFFFFFFF | |
328 | #define ACFG_ICFA2_D_VAL 0xFFFFFFFF | |
329 | #define ACFG_ICFB1_D_VAL 0xFFFFFFFF | |
330 | #define ACFG_ICFB2_D_VAL 0xFFFFFFFF | |
331 | #define ACFG_DR_D_VAL 0x00000000 | |
332 | #define ACFG_GIUS_D_VAL 0xFFFFFFFF | |
333 | #define ACFG_ICR1_D_VAL 0x00000000 | |
334 | #define ACFG_ICR2_D_VAL 0x00000000 | |
335 | #define ACFG_IMR_D_VAL 0x00000000 | |
336 | #define ACFG_GPR_D_VAL 0x00000000 | |
337 | #define ACFG_PUEN_D_VAL 0xFFFFFFFF | |
338 | ||
339 | #define ACFG_DDIR_E_VAL 0x00000000 | |
340 | #define ACFG_OCR1_E_VAL 0x00000000 | |
341 | #define ACFG_OCR2_E_VAL 0x00000000 | |
342 | #define ACFG_ICFA1_E_VAL 0xFFFFFFFF | |
343 | #define ACFG_ICFA2_E_VAL 0xFFFFFFFF | |
344 | #define ACFG_ICFB1_E_VAL 0xFFFFFFFF | |
345 | #define ACFG_ICFB2_E_VAL 0xFFFFFFFF | |
346 | #define ACFG_DR_E_VAL 0x00000000 | |
347 | #define ACFG_GIUS_E_VAL 0xFCFFCCF8 | |
348 | #define ACFG_ICR1_E_VAL 0x00000000 | |
349 | #define ACFG_ICR2_E_VAL 0x00000000 | |
350 | #define ACFG_IMR_E_VAL 0x00000000 | |
351 | #define ACFG_GPR_E_VAL 0x00000000 | |
352 | #define ACFG_PUEN_E_VAL 0xFFFFFFFF | |
353 | ||
354 | #define ACFG_DDIR_F_VAL 0x00000000 | |
355 | #define ACFG_OCR1_F_VAL 0x00000000 | |
356 | #define ACFG_OCR2_F_VAL 0x00000000 | |
357 | #define ACFG_ICFA1_F_VAL 0xFFFFFFFF | |
358 | #define ACFG_ICFA2_F_VAL 0xFFFFFFFF | |
359 | #define ACFG_ICFB1_F_VAL 0xFFFFFFFF | |
360 | #define ACFG_ICFB2_F_VAL 0xFFFFFFFF | |
361 | #define ACFG_DR_F_VAL 0x00000000 | |
362 | #define ACFG_GIUS_F_VAL 0xFF7F8000 | |
363 | #define ACFG_ICR1_F_VAL 0x00000000 | |
364 | #define ACFG_ICR2_F_VAL 0x00000000 | |
365 | #define ACFG_IMR_F_VAL 0x00000000 | |
366 | #define ACFG_GPR_F_VAL 0x00000000 | |
367 | #define ACFG_PUEN_F_VAL 0xFFFFFFFF | |
368 | ||
369 | /* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */ | |
370 | #define ACFG_GPCR_VAL 0x0003000F | |
371 | ||
372 | #define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN | |
373 | ||
374 | /* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */ | |
375 | #if (CONFIG_NR_DRAM_BANKS == 1) | |
376 | #define ACFG_FMCR_VAL 0xFFFFFFF9 | |
377 | #elif (CONFIG_NR_DRAM_BANKS == 2) | |
378 | #define ACFG_FMCR_VAL 0xFFFFFFFB | |
379 | #endif | |
380 | ||
381 | #define ACFG_AIPI1_PSR0_VAL 0x20040304 | |
382 | #define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB | |
383 | #define ACFG_AIPI2_PSR0_VAL 0x00000000 | |
384 | #define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF | |
385 | ||
386 | /* PCCR enable DMA FEC I2C1 IIM SDHC1 */ | |
387 | #define ACFG_PCCR0_VAL 0x05070410 | |
388 | #define ACFG_PCCR1_VAL 0xA14A0608 | |
389 | ||
390 | /* | |
391 | * From here, there should not be any user configuration. | |
392 | * All Equations are automatic | |
393 | */ | |
394 | ||
395 | /* fixme none integer value (7.5ns) => 2*hclock = 15ns */ | |
396 | #define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */ | |
397 | ||
398 | /* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/ | |
399 | #define CSCR_MASK 0x0300800D | |
400 | ||
401 | #define ACFG_CSCR_VAL \ | |
402 | (CSCR_MASK \ | |
403 | |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \ | |
404 | |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \ | |
405 | |((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8)) | |
406 | ||
407 | /* SSIx CLKO NFC H264 MSHC */ | |
408 | #define ACFG_PCDR0_VAL\ | |
409 | (((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \ | |
410 | |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \ | |
411 | |(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\ | |
412 | |(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\ | |
413 | |(((CONFIG_CLK0_DIV)&0x07)<<22)\ | |
414 | |(((CONFIG_CLK0_EN)&0x01)<<25)\ | |
415 | |(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26)) | |
416 | ||
417 | /* PERCLKx */ | |
418 | #define ACFG_PCDR1_VAL\ | |
419 | (((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \ | |
420 | |((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \ | |
421 | |((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \ | |
422 | |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24)) | |
423 | ||
424 | /* SDRAM controller programming Values */ | |
425 | #if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \ | |
426 | (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1)) | |
427 | #define REG_FIELD_SCL_VAL 3 | |
428 | #define REG_FIELD_SCLIMX_VAL 0 | |
429 | #else | |
430 | #define REG_FIELD_SCL_VAL\ | |
431 | ((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \ | |
432 | ACFG_2XHCLK_LGTH) | |
433 | #define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL | |
434 | #endif | |
435 | ||
436 | #if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH)) | |
437 | #define REG_FIELD_SRC_VAL 0 | |
438 | #else | |
439 | #define REG_FIELD_SRC_VAL\ | |
440 | ((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \ | |
441 | ACFG_2XHCLK_LGTH) | |
442 | #endif | |
443 | ||
444 | /* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/ | |
445 | #define REG_ESDCTL_BASE_CONFIG (0x80020485\ | |
446 | | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\ | |
447 | | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\ | |
448 | | (((ACFG_SDRAM_REFRESH)&0x7)<<13)) | |
449 | ||
450 | #define ACFG_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG) | |
451 | #define ACFG_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG) | |
452 | #define ACFG_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG) | |
453 | #define ACFG_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG) | |
454 | ||
455 | /* ESDRAMC Configuration Registers : force CL=3 to lpddr */ | |
456 | #define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\ | |
457 | | (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \ | |
458 | ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\ | |
459 | | (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\ | |
460 | | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \ | |
461 | ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \ | |
462 | | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\ | |
463 | | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\ | |
464 | | (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \ | |
465 | ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \ | |
466 | | (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ | |
467 | ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \ | |
468 | | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\ | |
469 | | (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ | |
470 | ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \ | |
471 | | (((REG_FIELD_SRC_VAL)&0x0F)<<0)) | |
472 | ||
473 | /* Issue Mode register Command to SDRAM */ | |
474 | #define ACFG_SDRAM_MODE_REGISTER_VAL\ | |
475 | ((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\ | |
476 | | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\ | |
477 | | ((0)<<(3)) /* sequentiql access */ \ | |
478 | /*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/) | |
479 | ||
480 | /* Issue Extended Mode register Command to SDRAM */ | |
481 | #define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\ | |
482 | ((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\ | |
483 | | (ACFG_SDRAM_DRIVE_STRENGH<<(5))\ | |
484 | | (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2))) | |
485 | ||
486 | /* Issue Precharge all Command to SDRAM */ | |
487 | #define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10) | |
488 | ||
489 | #endif /* __APF27_H */ |