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3d3befa7 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> | |
8 | * | |
9 | * (C) Copyright 2003 | |
10 | * Texas Instruments, <www.ti.com> | |
11 | * Kshitij Gupta <Kshitij@ti.com> | |
12 | * | |
13 | * (C) Copyright 2004 | |
14 | * ARM Ltd. | |
15 | * Philippe Robin, <philippe.robin@arm.com> | |
16 | * | |
3765b3e7 | 17 | * SPDX-License-Identifier: GPL-2.0+ |
3d3befa7 WD |
18 | */ |
19 | ||
20 | #include <common.h> | |
10efa024 | 21 | #include <netdev.h> |
7c045d0b | 22 | #include <asm/io.h> |
701ed16e | 23 | #include "arm-ebi.h" |
1dc26801 | 24 | #include "integrator-sc.h" |
10efa024 | 25 | |
d87080b7 WD |
26 | DECLARE_GLOBAL_DATA_PTR; |
27 | ||
3d3befa7 WD |
28 | void peripheral_power_enable (void); |
29 | ||
30 | #if defined(CONFIG_SHOW_BOOT_PROGRESS) | |
31 | void show_boot_progress(int progress) | |
32 | { | |
716c1dcb | 33 | printf("Boot reached stage %d\n", progress); |
3d3befa7 WD |
34 | } |
35 | #endif | |
36 | ||
37 | #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) | |
38 | ||
3d3befa7 WD |
39 | /* |
40 | * Miscellaneous platform dependent initialisations | |
41 | */ | |
42 | ||
43 | int board_init (void) | |
44 | { | |
701ed16e LW |
45 | u32 val; |
46 | ||
3d3befa7 | 47 | /* arch number of Integrator Board */ |
576afd4f JCPV |
48 | #ifdef CONFIG_ARCH_CINTEGRATOR |
49 | gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; | |
50 | #else | |
731215eb | 51 | gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR; |
576afd4f | 52 | #endif |
3d3befa7 WD |
53 | |
54 | /* adress of boot parameters */ | |
55 | gd->bd->bi_boot_params = 0x00000100; | |
56 | ||
bc54f309 WD |
57 | gd->flags = 0; |
58 | ||
0148e8cb WD |
59 | #ifdef CONFIG_CM_REMAP |
60 | extern void cm_remap(void); | |
61 | cm_remap(); /* remaps writeable memory to 0x00000000 */ | |
62 | #endif | |
716c1dcb | 63 | |
1dc26801 LW |
64 | #ifdef CONFIG_ARCH_CINTEGRATOR |
65 | /* | |
66 | * Flash protection on the Integrator/CP is in a simple register | |
67 | */ | |
68 | val = readl(CP_FLASHPROG); | |
69 | val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN); | |
70 | writel(val, CP_FLASHPROG); | |
71 | #else | |
701ed16e | 72 | /* |
1dc26801 LW |
73 | * The Integrator/AP has some special protection mechanisms |
74 | * for the external memories, first the External Bus Interface (EBI) | |
75 | * then the system controller (SC). | |
76 | * | |
701ed16e LW |
77 | * The system comes up with the flash memory non-writable and |
78 | * configuration locked. If we want U-Boot to be used for flash | |
79 | * access we cannot have the flash memory locked. | |
80 | */ | |
81 | writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG); | |
82 | val = readl(EBI_BASE + EBI_CSR1_REG); | |
83 | val &= EBI_CSR_WREN_MASK; | |
84 | val |= EBI_CSR_WREN_ENABLE; | |
85 | writel(val, EBI_BASE + EBI_CSR1_REG); | |
86 | writel(0, EBI_BASE + EBI_LOCK_REG); | |
87 | ||
1dc26801 LW |
88 | /* |
89 | * Set up the system controller to remove write protection from | |
90 | * the flash memory and enable Vpp | |
91 | */ | |
92 | writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS); | |
93 | #endif | |
94 | ||
3d3befa7 WD |
95 | icache_enable (); |
96 | ||
3d3befa7 WD |
97 | return 0; |
98 | } | |
99 | ||
3d3befa7 WD |
100 | int misc_init_r (void) |
101 | { | |
3d3befa7 WD |
102 | setenv("verify", "n"); |
103 | return (0); | |
104 | } | |
105 | ||
46b5ccbf LW |
106 | /* |
107 | * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot | |
108 | * from there, which means we cannot test the RAM underneath the ROM at this | |
109 | * point. It will be unmapped later on, when we are executing from the | |
110 | * relocated in RAM U-Boot. We simply assume that this RAM is usable if the | |
111 | * RAM on higher addresses works fine. | |
112 | */ | |
113 | #define REMAPPED_FLASH_SZ 0x40000 | |
114 | ||
3d3befa7 WD |
115 | int dram_init (void) |
116 | { | |
26c82638 | 117 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
0148e8cb WD |
118 | #ifdef CONFIG_CM_SPD_DETECT |
119 | { | |
120 | extern void dram_query(void); | |
7c045d0b LW |
121 | u32 cm_reg_sdram; |
122 | u32 sdram_shift; | |
0148e8cb WD |
123 | |
124 | dram_query(); /* Assembler accesses to CM registers */ | |
716c1dcb | 125 | /* Queries the SPD values */ |
0148e8cb WD |
126 | |
127 | /* Obtain the SDRAM size from the CM SDRAM register */ | |
128 | ||
7c045d0b | 129 | cm_reg_sdram = readl(CM_BASE + OS_SDRAM); |
716c1dcb WD |
130 | /* Register SDRAM size |
131 | * | |
132 | * 0xXXXXXXbbb000bb 16 MB | |
133 | * 0xXXXXXXbbb001bb 32 MB | |
134 | * 0xXXXXXXbbb010bb 64 MB | |
135 | * 0xXXXXXXbbb011bb 128 MB | |
136 | * 0xXXXXXXbbb100bb 256 MB | |
0148e8cb | 137 | * |
0148e8cb | 138 | */ |
7c045d0b | 139 | sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; |
46b5ccbf LW |
140 | gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + |
141 | REMAPPED_FLASH_SZ, | |
26c82638 | 142 | 0x01000000 << sdram_shift); |
0148e8cb | 143 | } |
26c82638 | 144 | #else |
46b5ccbf LW |
145 | gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + |
146 | REMAPPED_FLASH_SZ, | |
26c82638 | 147 | PHYS_SDRAM_1_SIZE); |
0148e8cb | 148 | #endif /* CM_SPD_DETECT */ |
46b5ccbf LW |
149 | /* We only have one bank of RAM, set it to whatever was detected */ |
150 | gd->bd->bi_dram[0].size = gd->ram_size; | |
0148e8cb | 151 | |
3d3befa7 WD |
152 | return 0; |
153 | } | |
74f4304e | 154 | |
7194ab80 | 155 | #ifdef CONFIG_CMD_NET |
10efa024 BW |
156 | int board_eth_init(bd_t *bis) |
157 | { | |
7194ab80 BW |
158 | int rc = 0; |
159 | #ifdef CONFIG_SMC91111 | |
160 | rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); | |
161 | #endif | |
7194ab80 | 162 | rc += pci_eth_init(bis); |
7194ab80 | 163 | return rc; |
10efa024 | 164 | } |
576afd4f | 165 | #endif |