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3d3befa7 WD |
1 | /* |
2 | * Board specific setup info | |
3 | * | |
4 | * (C) Copyright 2004, ARM Ltd. | |
5 | * Philippe Robin, <philippe.robin@arm.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
3d3befa7 WD |
8 | */ |
9 | ||
10 | #include <config.h> | |
11 | #include <version.h> | |
12 | ||
74f4304e WD |
13 | /* Reset using CM control register */ |
14 | .global reset_cpu | |
15 | reset_cpu: | |
16 | mov r0, #CM_BASE | |
17 | ldr r1,[r0,#OS_CTRL] | |
18 | orr r1,r1,#CMMASK_RESET | |
9b880bd4 | 19 | str r1,[r0,#OS_CTRL] |
74f4304e WD |
20 | |
21 | reset_failed: | |
22 | b reset_failed | |
716c1dcb | 23 | |
87cb6862 WD |
24 | /* Set up the platform, once the cpu has been initialized */ |
25 | .globl lowlevel_init | |
26 | lowlevel_init: | |
0148e8cb WD |
27 | /* If U-Boot has been run after the ARM boot monitor |
28 | * then all the necessary actions have been done | |
29 | * otherwise we are running from user flash mapped to 0x00000000 | |
30 | * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED -- | |
31 | * Changes to the (possibly soft) reset defaults of the processor | |
32 | * itself should be performed in cpu/arm<>/start.S | |
33 | * This function affects only the core module or board settings | |
34 | */ | |
716c1dcb | 35 | |
0148e8cb WD |
36 | #ifdef CONFIG_CM_INIT |
37 | /* CM has an initialization register | |
38 | * - bits in it are wired into test-chip pins to force | |
39 | * reset defaults | |
40 | * - may need to change its contents for U-Boot | |
41 | */ | |
716c1dcb | 42 | |
0148e8cb WD |
43 | /* set the desired CM specific value */ |
44 | mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */ | |
716c1dcb | 45 | |
0148e8cb WD |
46 | #if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) |
47 | orr r2,r2,#CMMASK_INIT_102 | |
48 | #else | |
716c1dcb | 49 | |
0148e8cb WD |
50 | #if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \ |
51 | !defined (CONFIG_CM940T) | |
716c1dcb | 52 | |
0148e8cb | 53 | #ifdef CONFIG_CM_MULTIPLE_SSRAM |
96782c63 | 54 | /* set simple mapping */ |
0148e8cb | 55 | and r2,r2,#CMMASK_MAP_SIMPLE |
96782c63 | 56 | #endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ |
716c1dcb | 57 | |
0148e8cb | 58 | #ifdef CONFIG_CM_TCRAM |
96782c63 | 59 | /* disable TCRAM */ |
0148e8cb | 60 | and r2,r2,#CMMASK_TCRAM_DISABLE |
96782c63 | 61 | #endif /* #ifdef CONFIG_CM_TCRAM */ |
716c1dcb | 62 | |
0148e8cb | 63 | #if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \ |
96782c63 | 64 | defined (CONFIG_CM1136JF_S) |
0148e8cb WD |
65 | |
66 | and r2,r2,#CMMASK_LE | |
716c1dcb | 67 | |
0148e8cb | 68 | #endif /* cpu with little endian initialization */ |
716c1dcb | 69 | |
0148e8cb | 70 | orr r2,r2,#CMMASK_CMxx6_COMMON |
716c1dcb | 71 | |
0148e8cb | 72 | #endif /* CMxx6 code */ |
716c1dcb | 73 | |
0148e8cb WD |
74 | #endif /* ARM102xxE value */ |
75 | ||
96782c63 | 76 | /* read CM_INIT */ |
0148e8cb WD |
77 | mov r0, #CM_BASE |
78 | ldr r1, [r0, #OS_INIT] | |
79 | /* check against desired bit setting */ | |
80 | and r3,r1,r2 | |
81 | cmp r3,r2 | |
82 | beq init_reg_OK | |
716c1dcb | 83 | |
0148e8cb | 84 | /* lock for change */ |
9b880bd4 WD |
85 | mov r3, #CMVAL_LOCK1 |
86 | add r3,r3,#CMVAL_LOCK2 | |
0148e8cb WD |
87 | str r3, [r0, #OS_LOCK] |
88 | /* set desired value */ | |
89 | orr r1,r1,r2 | |
90 | /* write & relock CM_INIT */ | |
91 | str r1, [r0, #OS_INIT] | |
92 | mov r1, #CMVAL_UNLOCK | |
93 | str r1, [r0, #OS_LOCK] | |
716c1dcb | 94 | |
0148e8cb WD |
95 | /* soft reset so new values used */ |
96 | b reset_cpu | |
716c1dcb | 97 | |
0148e8cb | 98 | init_reg_OK: |
716c1dcb | 99 | |
0148e8cb | 100 | #endif /* CONFIG_CM_INIT */ |
716c1dcb | 101 | |
0148e8cb | 102 | mov pc, lr |
716c1dcb | 103 | |
0148e8cb WD |
104 | #ifdef CONFIG_CM_SPD_DETECT |
105 | /* Fast memory is available for the DRAM data | |
106 | * - ensure it has been transferred, then summarize the data | |
107 | * into a CM register | |
108 | */ | |
109 | .globl dram_query | |
110 | dram_query: | |
111 | stmfd r13!,{r4-r6,lr} | |
96782c63 | 112 | /* set up SDRAM info */ |
0148e8cb WD |
113 | /* - based on example code from the CM User Guide */ |
114 | mov r0, #CM_BASE | |
716c1dcb | 115 | |
0148e8cb | 116 | readspdbit: |
96782c63 WD |
117 | ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */ |
118 | and r1, r1, #0x20 /* mask SPD bit (5) */ | |
119 | cmp r1, #0x20 /* test if set */ | |
0148e8cb | 120 | bne readspdbit |
716c1dcb | 121 | |
0148e8cb | 122 | setupsdram: |
96782c63 WD |
123 | add r0, r0, #OS_SPD /* address the copy of the SDP data */ |
124 | ldrb r1, [r0, #3] /* number of row address lines */ | |
125 | ldrb r2, [r0, #4] /* number of column address lines */ | |
126 | ldrb r3, [r0, #5] /* number of banks */ | |
127 | ldrb r4, [r0, #31] /* module bank density */ | |
128 | mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */ | |
129 | mov r5, r5, ASL#2 /* size in MB */ | |
130 | mov r0, #CM_BASE /* reload for later code */ | |
131 | cmp r5, #0x10 /* is it 16MB? */ | |
0148e8cb | 132 | bne not16 |
96782c63 | 133 | mov r6, #0x2 /* store size and CAS latency of 2 */ |
0148e8cb | 134 | b writesize |
716c1dcb | 135 | |
0148e8cb WD |
136 | not16: |
137 | cmp r5, #0x20 /* is it 32MB? */ | |
138 | bne not32 | |
139 | mov r6, #0x6 | |
140 | b writesize | |
716c1dcb | 141 | |
0148e8cb WD |
142 | not32: |
143 | cmp r5, #0x40 /* is it 64MB? */ | |
144 | bne not64 | |
145 | mov r6, #0xa | |
146 | b writesize | |
716c1dcb | 147 | |
0148e8cb WD |
148 | not64: |
149 | cmp r5, #0x80 /* is it 128MB? */ | |
150 | bne not128 | |
151 | mov r6, #0xe | |
152 | b writesize | |
716c1dcb | 153 | |
0148e8cb WD |
154 | not128: |
155 | /* if it is none of these sizes then it is either 256MB, or | |
156 | * there is no SDRAM fitted so default to 256MB | |
157 | */ | |
158 | mov r6, #0x12 | |
716c1dcb | 159 | |
0148e8cb WD |
160 | writesize: |
161 | mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */ | |
162 | orr r2, r1, r2, ASL#12 /* OR in column address lines */ | |
163 | orr r3, r2, r3, ASL#16 /* OR in number of banks */ | |
164 | orr r6, r6, r3 /* OR in size and CAS latency */ | |
165 | str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */ | |
716c1dcb | 166 | |
0148e8cb | 167 | #endif /* #ifdef CONFIG_CM_SPD_DETECT */ |
716c1dcb | 168 | |
0148e8cb WD |
169 | ldmfd r13!,{r4-r6,pc} /* back to caller */ |
170 | ||
171 | #ifdef CONFIG_CM_REMAP | |
172 | /* CM remap bit is operational | |
173 | * - use it to map writeable memory at 0x00000000, in place of flash | |
174 | */ | |
175 | .globl cm_remap | |
176 | cm_remap: | |
177 | stmfd r13!,{r4-r10,lr} | |
716c1dcb | 178 | |
0148e8cb WD |
179 | mov r0, #CM_BASE |
180 | ldr r1, [r0, #OS_CTRL] | |
181 | orr r1, r1, #CMMASK_REMAP /* set remap and led bits */ | |
182 | str r1, [r0, #OS_CTRL] | |
716c1dcb | 183 | |
96782c63 WD |
184 | /* Now 0x00000000 is writeable, replace the vectors */ |
185 | ldr r0, =_start /* r0 <- start of vectors */ | |
a46877cc | 186 | ldr r2, =_TEXT_BASE /* r2 <- past vectors */ |
96782c63 | 187 | sub r1,r1,r1 /* destination 0x00000000 */ |
716c1dcb | 188 | |
0148e8cb | 189 | copy_vec: |
96782c63 WD |
190 | ldmia r0!, {r3-r10} /* copy from source address [r0] */ |
191 | stmia r1!, {r3-r10} /* copy to target address [r1] */ | |
192 | cmp r0, r2 /* until source end address [r2] */ | |
0148e8cb | 193 | ble copy_vec |
716c1dcb | 194 | |
96782c63 | 195 | ldmfd r13!,{r4-r10,pc} /* back to caller */ |
716c1dcb | 196 | |
0148e8cb | 197 | #endif /* #ifdef CONFIG_CM_REMAP */ |