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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
b80e41ac MW |
2 | /* |
3 | * (C) Copyright 2002 | |
4 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
5 | * Marius Groeger <mgroeger@sysgo.de> | |
6 | * | |
7 | * (C) Copyright 2002 | |
8 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> | |
9 | * | |
10 | * (C) Copyright 2003 | |
11 | * Texas Instruments, <www.ti.com> | |
12 | * Kshitij Gupta <Kshitij@ti.com> | |
13 | * | |
14 | * (C) Copyright 2004 | |
15 | * ARM Ltd. | |
16 | * Philippe Robin, <philippe.robin@arm.com> | |
b80e41ac MW |
17 | */ |
18 | #include <common.h> | |
62270f43 | 19 | #include <cpu_func.h> |
9b4a205f | 20 | #include <init.h> |
10ed93dc JR |
21 | #include <malloc.h> |
22 | #include <errno.h> | |
90526e9f | 23 | #include <net.h> |
b80e41ac MW |
24 | #include <netdev.h> |
25 | #include <asm/io.h> | |
c62db35d | 26 | #include <asm/mach-types.h> |
b80e41ac MW |
27 | #include <asm/arch/systimer.h> |
28 | #include <asm/arch/sysctrl.h> | |
29 | #include <asm/arch/wdt.h> | |
a6f479cd | 30 | #include "../drivers/mmc/arm_pl180_mmci.h" |
b80e41ac | 31 | |
cd4f46e1 | 32 | static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01; |
b80e41ac MW |
33 | static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; |
34 | ||
35 | static void flash__init(void); | |
36 | static void vexpress_timer_init(void); | |
37 | DECLARE_GLOBAL_DATA_PTR; | |
38 | ||
39 | #if defined(CONFIG_SHOW_BOOT_PROGRESS) | |
40 | void show_boot_progress(int progress) | |
41 | { | |
42 | printf("Boot reached stage %d\n", progress); | |
43 | } | |
44 | #endif | |
45 | ||
46 | static inline void delay(ulong loops) | |
47 | { | |
48 | __asm__ volatile ("1:\n" | |
49 | "subs %0, %1, #1\n" | |
50 | "bne 1b" : "=r" (loops) : "0" (loops)); | |
51 | } | |
52 | ||
53 | int board_init(void) | |
54 | { | |
55 | gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; | |
56 | gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; | |
57 | gd->flags = 0; | |
58 | ||
59 | icache_enable(); | |
60 | flash__init(); | |
61 | vexpress_timer_init(); | |
62 | ||
63 | return 0; | |
64 | } | |
65 | ||
66 | int board_eth_init(bd_t *bis) | |
67 | { | |
68 | int rc = 0; | |
69 | #ifdef CONFIG_SMC911X | |
70 | rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); | |
71 | #endif | |
72 | return rc; | |
73 | } | |
74 | ||
f0c64526 MW |
75 | int cpu_mmc_init(bd_t *bis) |
76 | { | |
77 | int rc = 0; | |
10ed93dc | 78 | (void) bis; |
f0c64526 | 79 | #ifdef CONFIG_ARM_PL180_MMCI |
10ed93dc | 80 | struct pl180_mmc_host *host; |
cb0060e8 | 81 | struct mmc *mmc; |
10ed93dc JR |
82 | |
83 | host = malloc(sizeof(struct pl180_mmc_host)); | |
84 | if (!host) | |
85 | return -ENOMEM; | |
86 | memset(host, 0, sizeof(*host)); | |
87 | ||
88 | strcpy(host->name, "MMC"); | |
89 | host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; | |
90 | host->pwr_init = INIT_PWR; | |
91 | host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; | |
92 | host->voltages = VOLTAGE_WINDOW_MMC; | |
93 | host->caps = 0; | |
94 | host->clock_in = ARM_MCLK; | |
95 | host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); | |
96 | host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; | |
cb0060e8 | 97 | rc = arm_pl180_mmci_init(host, &mmc); |
f0c64526 MW |
98 | #endif |
99 | return rc; | |
100 | } | |
101 | ||
b80e41ac MW |
102 | static void flash__init(void) |
103 | { | |
104 | /* Setup the sytem control register to allow writing to flash */ | |
105 | writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN, | |
106 | &sysctrl_base->scflashctrl); | |
107 | } | |
108 | ||
109 | int dram_init(void) | |
110 | { | |
9d37cf31 MW |
111 | gd->ram_size = |
112 | get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); | |
b80e41ac MW |
113 | return 0; |
114 | } | |
115 | ||
76b00aca | 116 | int dram_init_banksize(void) |
b80e41ac MW |
117 | { |
118 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
9d37cf31 MW |
119 | gd->bd->bi_dram[0].size = |
120 | get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); | |
b80e41ac | 121 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
9d37cf31 MW |
122 | gd->bd->bi_dram[1].size = |
123 | get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); | |
76b00aca SG |
124 | |
125 | return 0; | |
b80e41ac MW |
126 | } |
127 | ||
b80e41ac MW |
128 | /* |
129 | * Start timer: | |
130 | * Setup a 32 bit timer, running at 1KHz | |
131 | * Versatile Express Motherboard provides 1 MHz timer | |
132 | */ | |
133 | static void vexpress_timer_init(void) | |
134 | { | |
135 | /* | |
136 | * Set clock frequency in system controller: | |
137 | * VEXPRESS_REFCLK is 32KHz | |
138 | * VEXPRESS_TIMCLK is 1MHz | |
139 | */ | |
140 | writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL | | |
141 | SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL | | |
142 | readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl); | |
143 | ||
144 | /* | |
145 | * Set Timer0 to be: | |
146 | * Enabled, free running, no interrupt, 32-bit, wrapping | |
147 | */ | |
148 | writel(SYSTIMER_RELOAD, &systimer_base->timer0load); | |
149 | writel(SYSTIMER_RELOAD, &systimer_base->timer0value); | |
9b58a3f6 RH |
150 | writel(SYSTIMER_EN | SYSTIMER_32BIT | |
151 | readl(&systimer_base->timer0control), | |
b80e41ac | 152 | &systimer_base->timer0control); |
b80e41ac MW |
153 | } |
154 | ||
cd4f46e1 RH |
155 | int v2m_cfg_write(u32 devfn, u32 data) |
156 | { | |
157 | /* Configuration interface broken? */ | |
158 | u32 val; | |
159 | ||
160 | devfn |= SYS_CFG_START | SYS_CFG_WRITE; | |
161 | ||
162 | val = readl(V2M_SYS_CFGSTAT); | |
163 | writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT); | |
164 | ||
165 | writel(data, V2M_SYS_CFGDATA); | |
166 | writel(devfn, V2M_SYS_CFGCTRL); | |
167 | ||
168 | do { | |
169 | val = readl(V2M_SYS_CFGSTAT); | |
170 | } while (val == 0); | |
171 | ||
172 | return !!(val & SYS_CFG_ERR); | |
173 | } | |
174 | ||
b80e41ac MW |
175 | /* Use the ARM Watchdog System to cause reset */ |
176 | void reset_cpu(ulong addr) | |
177 | { | |
cd4f46e1 RH |
178 | if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) |
179 | printf("Unable to reboot\n"); | |
b80e41ac MW |
180 | } |
181 | ||
b80e41ac MW |
182 | void lowlevel_init(void) |
183 | { | |
184 | } | |
185 | ||
186 | ulong get_board_rev(void){ | |
187 | return readl((u32 *)SYS_ID); | |
188 | } | |
d721a3a7 | 189 | |
104d6fb6 | 190 | #ifdef CONFIG_ARMV7_NONSEC |
e261c83a AP |
191 | /* Setting the address at which secondary cores start from. |
192 | * Versatile Express uses one address for all cores, so ignore corenr | |
193 | */ | |
194 | void smp_set_core_boot_addr(unsigned long addr, int corenr) | |
195 | { | |
196 | /* The SYSFLAGS register on VExpress needs to be cleared first | |
197 | * by writing to the next address, since any writes to the address | |
198 | * at offset 0 will only be ORed in | |
199 | */ | |
200 | writel(~0, CONFIG_SYSFLAGS_ADDR + 4); | |
201 | writel(addr, CONFIG_SYSFLAGS_ADDR); | |
202 | } | |
203 | #endif |