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b80e41ac MW |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> | |
8 | * | |
9 | * (C) Copyright 2003 | |
10 | * Texas Instruments, <www.ti.com> | |
11 | * Kshitij Gupta <Kshitij@ti.com> | |
12 | * | |
13 | * (C) Copyright 2004 | |
14 | * ARM Ltd. | |
15 | * Philippe Robin, <philippe.robin@arm.com> | |
16 | * | |
1a459660 | 17 | * SPDX-License-Identifier: GPL-2.0+ |
b80e41ac MW |
18 | */ |
19 | #include <common.h> | |
10ed93dc JR |
20 | #include <malloc.h> |
21 | #include <errno.h> | |
b80e41ac MW |
22 | #include <netdev.h> |
23 | #include <asm/io.h> | |
c62db35d | 24 | #include <asm/mach-types.h> |
b80e41ac MW |
25 | #include <asm/arch/systimer.h> |
26 | #include <asm/arch/sysctrl.h> | |
27 | #include <asm/arch/wdt.h> | |
a6f479cd | 28 | #include "../drivers/mmc/arm_pl180_mmci.h" |
b80e41ac | 29 | |
cd4f46e1 | 30 | static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01; |
b80e41ac MW |
31 | static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE; |
32 | ||
33 | static void flash__init(void); | |
34 | static void vexpress_timer_init(void); | |
35 | DECLARE_GLOBAL_DATA_PTR; | |
36 | ||
37 | #if defined(CONFIG_SHOW_BOOT_PROGRESS) | |
38 | void show_boot_progress(int progress) | |
39 | { | |
40 | printf("Boot reached stage %d\n", progress); | |
41 | } | |
42 | #endif | |
43 | ||
44 | static inline void delay(ulong loops) | |
45 | { | |
46 | __asm__ volatile ("1:\n" | |
47 | "subs %0, %1, #1\n" | |
48 | "bne 1b" : "=r" (loops) : "0" (loops)); | |
49 | } | |
50 | ||
51 | int board_init(void) | |
52 | { | |
53 | gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; | |
54 | gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS; | |
55 | gd->flags = 0; | |
56 | ||
57 | icache_enable(); | |
58 | flash__init(); | |
59 | vexpress_timer_init(); | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
64 | int board_eth_init(bd_t *bis) | |
65 | { | |
66 | int rc = 0; | |
67 | #ifdef CONFIG_SMC911X | |
68 | rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); | |
69 | #endif | |
70 | return rc; | |
71 | } | |
72 | ||
f0c64526 MW |
73 | int cpu_mmc_init(bd_t *bis) |
74 | { | |
75 | int rc = 0; | |
10ed93dc | 76 | (void) bis; |
f0c64526 | 77 | #ifdef CONFIG_ARM_PL180_MMCI |
10ed93dc JR |
78 | struct pl180_mmc_host *host; |
79 | ||
80 | host = malloc(sizeof(struct pl180_mmc_host)); | |
81 | if (!host) | |
82 | return -ENOMEM; | |
83 | memset(host, 0, sizeof(*host)); | |
84 | ||
85 | strcpy(host->name, "MMC"); | |
86 | host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; | |
87 | host->pwr_init = INIT_PWR; | |
88 | host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; | |
89 | host->voltages = VOLTAGE_WINDOW_MMC; | |
90 | host->caps = 0; | |
91 | host->clock_in = ARM_MCLK; | |
92 | host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); | |
93 | host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; | |
94 | rc = arm_pl180_mmci_init(host); | |
f0c64526 MW |
95 | #endif |
96 | return rc; | |
97 | } | |
98 | ||
b80e41ac MW |
99 | static void flash__init(void) |
100 | { | |
101 | /* Setup the sytem control register to allow writing to flash */ | |
102 | writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN, | |
103 | &sysctrl_base->scflashctrl); | |
104 | } | |
105 | ||
106 | int dram_init(void) | |
107 | { | |
9d37cf31 MW |
108 | gd->ram_size = |
109 | get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); | |
b80e41ac MW |
110 | return 0; |
111 | } | |
112 | ||
76b00aca | 113 | int dram_init_banksize(void) |
b80e41ac MW |
114 | { |
115 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
9d37cf31 MW |
116 | gd->bd->bi_dram[0].size = |
117 | get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); | |
b80e41ac | 118 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
9d37cf31 MW |
119 | gd->bd->bi_dram[1].size = |
120 | get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); | |
76b00aca SG |
121 | |
122 | return 0; | |
b80e41ac MW |
123 | } |
124 | ||
b80e41ac MW |
125 | /* |
126 | * Start timer: | |
127 | * Setup a 32 bit timer, running at 1KHz | |
128 | * Versatile Express Motherboard provides 1 MHz timer | |
129 | */ | |
130 | static void vexpress_timer_init(void) | |
131 | { | |
132 | /* | |
133 | * Set clock frequency in system controller: | |
134 | * VEXPRESS_REFCLK is 32KHz | |
135 | * VEXPRESS_TIMCLK is 1MHz | |
136 | */ | |
137 | writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL | | |
138 | SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL | | |
139 | readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl); | |
140 | ||
141 | /* | |
142 | * Set Timer0 to be: | |
143 | * Enabled, free running, no interrupt, 32-bit, wrapping | |
144 | */ | |
145 | writel(SYSTIMER_RELOAD, &systimer_base->timer0load); | |
146 | writel(SYSTIMER_RELOAD, &systimer_base->timer0value); | |
9b58a3f6 RH |
147 | writel(SYSTIMER_EN | SYSTIMER_32BIT | |
148 | readl(&systimer_base->timer0control), | |
b80e41ac | 149 | &systimer_base->timer0control); |
b80e41ac MW |
150 | } |
151 | ||
cd4f46e1 RH |
152 | int v2m_cfg_write(u32 devfn, u32 data) |
153 | { | |
154 | /* Configuration interface broken? */ | |
155 | u32 val; | |
156 | ||
157 | devfn |= SYS_CFG_START | SYS_CFG_WRITE; | |
158 | ||
159 | val = readl(V2M_SYS_CFGSTAT); | |
160 | writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT); | |
161 | ||
162 | writel(data, V2M_SYS_CFGDATA); | |
163 | writel(devfn, V2M_SYS_CFGCTRL); | |
164 | ||
165 | do { | |
166 | val = readl(V2M_SYS_CFGSTAT); | |
167 | } while (val == 0); | |
168 | ||
169 | return !!(val & SYS_CFG_ERR); | |
170 | } | |
171 | ||
b80e41ac MW |
172 | /* Use the ARM Watchdog System to cause reset */ |
173 | void reset_cpu(ulong addr) | |
174 | { | |
cd4f46e1 RH |
175 | if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) |
176 | printf("Unable to reboot\n"); | |
b80e41ac MW |
177 | } |
178 | ||
b80e41ac MW |
179 | void lowlevel_init(void) |
180 | { | |
181 | } | |
182 | ||
183 | ulong get_board_rev(void){ | |
184 | return readl((u32 *)SYS_ID); | |
185 | } | |
d721a3a7 | 186 | |
104d6fb6 | 187 | #ifdef CONFIG_ARMV7_NONSEC |
e261c83a AP |
188 | /* Setting the address at which secondary cores start from. |
189 | * Versatile Express uses one address for all cores, so ignore corenr | |
190 | */ | |
191 | void smp_set_core_boot_addr(unsigned long addr, int corenr) | |
192 | { | |
193 | /* The SYSFLAGS register on VExpress needs to be cleared first | |
194 | * by writing to the next address, since any writes to the address | |
195 | * at offset 0 will only be ORed in | |
196 | */ | |
197 | writel(~0, CONFIG_SYSFLAGS_ADDR + 4); | |
198 | writel(addr, CONFIG_SYSFLAGS_ADDR); | |
199 | } | |
200 | #endif |