[people/ms/u-boot.git] / board / armltd / vexpress64 / vexpress64.c

/*
 * (C) Copyright 2013
 * David Feng <fenghua@phytium.com.cn>
 * Sharma Bhupesh <bhupesh.sharma@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <dm/platdata.h>
#include <dm/platform_data/serial_pl01x.h>
#include "pcie.h"

DECLARE_GLOBAL_DATA_PTR;

static const struct pl01x_serial_platdata serial_platdata = {
	.base = V2M_UART0,
	.type = TYPE_PL011,
	.clock = CONFIG_PL011_CLOCK,
};

U_BOOT_DEVICE(vexpress_serials) = {
	.name = "serial_pl01x",
	.platdata = &serial_platdata,
};

/* This function gets replaced by platforms supporting PCIe.
 * The replacement function, eg. on Juno, initialises the PCIe bus.
 */
__weak void vexpress64_pcie_init(void)
{
}

int board_init(void)
{
	vexpress64_pcie_init();
	return 0;
}

int dram_init(void)
{
	gd->ram_size = PHYS_SDRAM_1_SIZE;
	return 0;
}

void dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#ifdef PHYS_SDRAM_2
	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
}

/*
 * Board specific reset that is system reset.
 */
void reset_cpu(ulong addr)
{
}

/*
 * Board specific ethernet initialization routine.
 */
int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_SMC91111
	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
#endif
#ifdef CONFIG_SMC911X
	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
	return rc;
}
Commit	Line	Data
12916829 DF	1	/*
	2	* (C) Copyright 2013
	3	* David Feng <fenghua@phytium.com.cn>
	4	* Sharma Bhupesh <bhupesh.sharma@freescale.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8	#include <common.h>
	9	#include <malloc.h>
	10	#include <errno.h>
	11	#include <netdev.h>
	12	#include <asm/io.h>
	13	#include <linux/compiler.h>
d8bafe13 DF	14	#include <dm/platdata.h>
d8bafe13 DF	15	#include <dm/platform_data/serial_pl01x.h>
2fdc9b74	16	#include "pcie.h"
12916829 DF	17
	18	DECLARE_GLOBAL_DATA_PTR;
	19
d8bafe13 DF	20	static const struct pl01x_serial_platdata serial_platdata = {
	21	.base = V2M_UART0,
	22	.type = TYPE_PL011,
d280ea00	23	.clock = CONFIG_PL011_CLOCK,
d8bafe13 DF	24	};
	25
	26	U_BOOT_DEVICE(vexpress_serials) = {
	27	.name = "serial_pl01x",
	28	.platdata = &serial_platdata,
	29	};
	30
bc8d3bc0 RH	31	/* This function gets replaced by platforms supporting PCIe.
	32	* The replacement function, eg. on Juno, initialises the PCIe bus.
	33	*/
	34	__weak void vexpress64_pcie_init(void)
	35	{
	36	}
	37
12916829 DF	38	int board_init(void)
12916829 DF	39	{
2fdc9b74	40	vexpress64_pcie_init();
12916829 DF	41	return 0;
	42	}
	43
	44	int dram_init(void)
	45	{
12916829 DF	46	gd->ram_size = PHYS_SDRAM_1_SIZE;
	47	return 0;
	48	}
	49
2d0cee1c LD	50	void dram_init_banksize(void)
	51	{
	52	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	53	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
2c2b2183	54	#ifdef PHYS_SDRAM_2
2d0cee1c LD	55	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
2d0cee1c LD	56	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
2c2b2183	57	#endif
2d0cee1c LD	58	}
2d0cee1c LD	59
12916829 DF	60	/*
	61	* Board specific reset that is system reset.
	62	*/
	63	void reset_cpu(ulong addr)
	64	{
	65	}
	66
	67	/*
	68	* Board specific ethernet initialization routine.
	69	*/
	70	int board_eth_init(bd_t *bis)
	71	{
	72	int rc = 0;
	73	#ifdef CONFIG_SMC91111
	74	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
b31f9d7a LW	75	#endif
	76	#ifdef CONFIG_SMC911X
	77	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
12916829 DF	78	#endif
	79	return rc;
	80	}