[thirdparty/u-boot.git] / board / atmel / at91sam9rlek / at91sam9rlek.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91sam9rl.h>
#include <asm/arch/at91sam9rl_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>

#include <lcd.h>
#include <atmel_lcdc.h>
#include <atmel_mci.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_CMD_NAND
static void at91sam9rlek_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	unsigned long csa;

	/* Enable CS3 */
	csa = readl(&matrix->ebicsa);
	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;

	writel(csa, &matrix->ebicsa);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
		&smc->cs[3].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		AT91_SMC_MODE_DBW_8 |
#endif
		AT91_SMC_MODE_TDF_CYCLE(2),
		&smc->cs[3].mode);

	at91_periph_clk_enable(ATMEL_ID_PIOD);

	/* Configure RDY/BSY */
	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);

	at91_set_A_periph(AT91_PIN_PB4, 0);		/* NANDOE */
	at91_set_A_periph(AT91_PIN_PB5, 0);		/* NANDWE */
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	.vl_col =		240,
	.vl_row =		320,
	.vl_clk =		4965000,
	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
				ATMEL_LCDC_INVFRAME_INVERTED,
	.vl_bpix =		3,
	.vl_tft =		1,
	.vl_hsync_len =		5,
	.vl_left_margin =	1,
	.vl_right_margin =	33,
	.vl_vsync_len =		1,
	.vl_upper_margin =	1,
	.vl_lower_margin =	0,
	.mmio =			ATMEL_BASE_LCDC,
};

void lcd_enable(void)
{
	at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
}

void lcd_disable(void)
{
	at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
}
static void at91sam9rlek_lcd_hw_init(void)
{
	at91_set_B_periph(AT91_PIN_PC1, 0);	/* LCDPWR */
	at91_set_A_periph(AT91_PIN_PC5, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDDEN */
	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDCC */
	at91_set_B_periph(AT91_PIN_PC9, 0);	/* LCDD3 */
	at91_set_B_periph(AT91_PIN_PC10, 0);	/* LCDD4 */
	at91_set_B_periph(AT91_PIN_PC11, 0);	/* LCDD5 */
	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD6 */
	at91_set_B_periph(AT91_PIN_PC13, 0);	/* LCDD7 */
	at91_set_B_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
	at91_set_B_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD13 */
	at91_set_B_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
	at91_set_B_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
	at91_set_B_periph(AT91_PIN_PC20, 0);	/* LCDD18 */
	at91_set_B_periph(AT91_PIN_PC21, 0);	/* LCDD19 */
	at91_set_B_periph(AT91_PIN_PC22, 0);	/* LCDD20 */
	at91_set_B_periph(AT91_PIN_PC23, 0);	/* LCDD21 */
	at91_set_B_periph(AT91_PIN_PC24, 0);	/* LCDD22 */
	at91_set_B_periph(AT91_PIN_PC25, 0);	/* LCDD23 */

	at91_periph_clk_enable(ATMEL_ID_LCDC);
}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

void lcd_show_board_info(void)
{
	ulong dram_size, nand_size;
	int i;
	char temp[32];

	lcd_printf ("%s\n", U_BOOT_VERSION);
	lcd_printf ("(C) 2008 ATMEL Corp\n");
	lcd_printf ("at91support@atmel.com\n");
	lcd_printf ("%s CPU at %s MHz\n",
		ATMEL_CPU_NAME,
		strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;
	nand_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i]->size;
	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
		dram_size >> 20,
		nand_size >> 20 );
}
#endif /* CONFIG_LCD_INFO */
#endif

#ifdef CONFIG_GENERIC_ATMEL_MCI
int board_mmc_init(bd_t *bis)
{
	at91_mci_hw_init();

	return atmel_mci_init((void *)ATMEL_BASE_MCI);
}
#endif

int board_early_init_f(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOC);
	at91_periph_clk_enable(ATMEL_ID_PIOD);

	return 0;
}

int board_init(void)
{
	/* arch number of AT91SAM9RLEK-Board */
	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	at91_seriald_hw_init();
#ifdef CONFIG_CMD_NAND
	at91sam9rlek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_LCD
	at91sam9rlek_lcd_hw_init();
#endif
	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size(
		(void *)CONFIG_SYS_SDRAM_BASE,
		CONFIG_SYS_SDRAM_SIZE);
	return 0;
}
Commit	Line	Data
2118ebb4 SP	1	/*
2118ebb4 SP	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
2118ebb4 SP	4	* Lead Tech Design <www.leadtechdesign.com>
2118ebb4 SP	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
2118ebb4 SP	7	*/
	8
	9	#include <common.h>
21d671d0	10	#include <asm/io.h>
2118ebb4 SP	11	#include <asm/arch/at91sam9rl.h>
	12	#include <asm/arch/at91sam9rl_matrix.h>
	13	#include <asm/arch/at91sam9_smc.h>
1332a2a0	14	#include <asm/arch/at91_common.h>
2118ebb4	15	#include <asm/arch/at91_rstc.h>
dc39ae95	16	#include <asm/arch/clk.h>
2118ebb4	17	#include <asm/arch/gpio.h>
21d671d0	18
761c70b8 SP	19	#include <lcd.h>
761c70b8 SP	20	#include <atmel_lcdc.h>
111ec4c6	21	#include <atmel_mci.h>
2118ebb4 SP	22	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
	23	#include <net.h>
	24	#endif
	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
	28	/* ------------------------------------------------------------------------- */
	29	/*
	30	* Miscelaneous platform dependent initialisations
	31	*/
	32
2118ebb4 SP	33	#ifdef CONFIG_CMD_NAND
	34	static void at91sam9rlek_nand_hw_init(void)
	35	{
21d671d0 XH	36	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
21d671d0 XH	37	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
2118ebb4 SP	38	unsigned long csa;
	39
	40	/* Enable CS3 */
21d671d0 XH	41	csa = readl(&matrix->ebicsa);
	42	csa \|= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	43
	44	writel(csa, &matrix->ebicsa);
2118ebb4 SP	45
2118ebb4 SP	46	/* Configure SMC CS3 for NAND/SmartMedia */
21d671d0 XH	47	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
	48	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
	49	&smc->cs[3].setup);
	50	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	51	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	52	&smc->cs[3].pulse);
	53	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	54	&smc->cs[3].cycle);
	55	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	56	AT91_SMC_MODE_EXNW_DISABLE \|
6d0f6bcf	57	#ifdef CONFIG_SYS_NAND_DBW_16
21d671d0	58	AT91_SMC_MODE_DBW_16 \|
6d0f6bcf	59	#else /* CONFIG_SYS_NAND_DBW_8 */
21d671d0	60	AT91_SMC_MODE_DBW_8 \|
2118ebb4	61	#endif
21d671d0 XH	62	AT91_SMC_MODE_TDF_CYCLE(2),
21d671d0 XH	63	&smc->cs[3].mode);
2118ebb4	64
70341e2e	65	at91_periph_clk_enable(ATMEL_ID_PIOD);
2118ebb4 SP	66
2118ebb4 SP	67	/* Configure RDY/BSY */
74c076d6	68	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
2118ebb4 SP	69
2118ebb4 SP	70	/* Enable NandFlash */
74c076d6	71	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
2118ebb4 SP	72
	73	at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
	74	at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
	75	}
	76	#endif
	77
761c70b8 SP	78	#ifdef CONFIG_LCD
761c70b8 SP	79	vidinfo_t panel_info = {
c346e466 JH	80	.vl_col = 240,
	81	.vl_row = 320,
	82	.vl_clk = 4965000,
	83	.vl_sync = ATMEL_LCDC_INVLINE_INVERTED \|
	84	ATMEL_LCDC_INVFRAME_INVERTED,
	85	.vl_bpix = 3,
	86	.vl_tft = 1,
	87	.vl_hsync_len = 5,
	88	.vl_left_margin = 1,
	89	.vl_right_margin = 33,
	90	.vl_vsync_len = 1,
	91	.vl_upper_margin = 1,
	92	.vl_lower_margin = 0,
	93	.mmio = ATMEL_BASE_LCDC,
761c70b8 SP	94	};
	95
	96	void lcd_enable(void)
	97	{
	98	at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
	99	}
	100
	101	void lcd_disable(void)
	102	{
	103	at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
	104	}
	105	static void at91sam9rlek_lcd_hw_init(void)
	106	{
	107	at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
	108	at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
	109	at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
	110	at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
	111	at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
	112	at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
	113	at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
	114	at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
	115	at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
	116	at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
	117	at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
	118	at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
	119	at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
	120	at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
	121	at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
	122	at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
	123	at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
	124	at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
	125	at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
	126	at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
	127	at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
	128
70341e2e	129	at91_periph_clk_enable(ATMEL_ID_LCDC);
761c70b8	130	}
6b59e03e HS	131
	132	#ifdef CONFIG_LCD_INFO
	133	#include <nand.h>
	134	#include <version.h>
	135
	136	void lcd_show_board_info(void)
	137	{
	138	ulong dram_size, nand_size;
	139	int i;
	140	char temp[32];
	141
	142	lcd_printf ("%s\n", U_BOOT_VERSION);
	143	lcd_printf ("(C) 2008 ATMEL Corp\n");
	144	lcd_printf ("at91support@atmel.com\n");
	145	lcd_printf ("%s CPU at %s MHz\n",
21d671d0	146	ATMEL_CPU_NAME,
dc39ae95	147	strmhz(temp, get_cpu_clk_rate()));
6b59e03e HS	148
	149	dram_size = 0;
	150	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	151	dram_size += gd->bd->bi_dram[i].size;
	152	nand_size = 0;
	153	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
b616d9b0	154	nand_size += nand_info[i]->size;
6b59e03e HS	155	lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
	156	dram_size >> 20,
	157	nand_size >> 20 );
	158	}
	159	#endif /* CONFIG_LCD_INFO */
761c70b8 SP	160	#endif
761c70b8 SP	161
111ec4c6 WJ	162	#ifdef CONFIG_GENERIC_ATMEL_MCI
	163	int board_mmc_init(bd_t *bis)
	164	{
	165	at91_mci_hw_init();
	166
	167	return atmel_mci_init((void *)ATMEL_BASE_MCI);
	168	}
	169	#endif
	170
21d671d0 XH	171	int board_early_init_f(void)
21d671d0 XH	172	{
70341e2e WY	173	at91_periph_clk_enable(ATMEL_ID_PIOA);
	174	at91_periph_clk_enable(ATMEL_ID_PIOB);
	175	at91_periph_clk_enable(ATMEL_ID_PIOC);
	176	at91_periph_clk_enable(ATMEL_ID_PIOD);
21d671d0 XH	177
	178	return 0;
	179	}
761c70b8	180
2118ebb4 SP	181	int board_init(void)
2118ebb4 SP	182	{
2118ebb4 SP	183	/* arch number of AT91SAM9RLEK-Board */
	184	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
	185	/* adress of boot parameters */
21d671d0	186	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
2118ebb4	187
21d671d0	188	at91_seriald_hw_init();
2118ebb4 SP	189	#ifdef CONFIG_CMD_NAND
	190	at91sam9rlek_nand_hw_init();
	191	#endif
	192	#ifdef CONFIG_HAS_DATAFLASH
7ebafb7e	193	at91_spi0_hw_init(1 << 0);
761c70b8 SP	194	#endif
	195	#ifdef CONFIG_LCD
	196	at91sam9rlek_lcd_hw_init();
2118ebb4 SP	197	#endif
	198	return 0;
	199	}
	200
	201	int dram_init(void)
	202	{
21d671d0 XH	203	gd->ram_size = get_ram_size(
	204	(void *)CONFIG_SYS_SDRAM_BASE,
	205	CONFIG_SYS_SDRAM_SIZE);
2118ebb4 SP	206	return 0;
2118ebb4 SP	207	}