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Commit | Line | Data |
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6b443944 HS |
1 | /* |
2 | * Copyright (C) 2006 Atmel Corporation | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
6b443944 HS |
5 | */ |
6 | #include <common.h> | |
7 | ||
8 | #include <asm/io.h> | |
9 | #include <asm/sdram.h> | |
d38da537 | 10 | #include <asm/arch/clk.h> |
6b443944 | 11 | #include <asm/arch/gpio.h> |
44453b25 | 12 | #include <asm/arch/hmatrix.h> |
1f36f73f | 13 | #include <asm/arch/mmu.h> |
ab0df36f | 14 | #include <asm/arch/portmux.h> |
89973f8a | 15 | #include <netdev.h> |
6b443944 HS |
16 | |
17 | DECLARE_GLOBAL_DATA_PTR; | |
18 | ||
1f36f73f HS |
19 | struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { |
20 | { | |
e9ed41cc AB |
21 | .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, |
22 | .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, | |
23 | .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) | |
1f36f73f HS |
24 | | MMU_VMR_CACHE_NONE, |
25 | }, { | |
e9ed41cc AB |
26 | .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, |
27 | .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, | |
28 | .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) | |
1f36f73f HS |
29 | | MMU_VMR_CACHE_WRBACK, |
30 | }, | |
31 | }; | |
32 | ||
a23e277c HS |
33 | static const struct sdram_config sdram_config = { |
34 | .data_bits = SDRAM_DATA_16BIT, | |
6b443944 HS |
35 | .row_bits = 13, |
36 | .col_bits = 9, | |
37 | .bank_bits = 2, | |
38 | .cas = 3, | |
39 | .twr = 2, | |
40 | .trc = 7, | |
41 | .trp = 2, | |
42 | .trcd = 2, | |
43 | .tras = 5, | |
44 | .txsr = 5, | |
d38da537 HS |
45 | /* 7.81 us */ |
46 | .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, | |
6b443944 HS |
47 | }; |
48 | ||
49 | int board_early_init_f(void) | |
50 | { | |
44453b25 HS |
51 | /* Enable SDRAM in the EBI mux */ |
52 | hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); | |
6b443944 | 53 | |
ab0df36f | 54 | portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH); |
18667860 AB |
55 | sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); |
56 | ||
ab0df36f | 57 | portmux_enable_usart1(PORTMUX_DRIVE_MIN); |
6b443944 HS |
58 | |
59 | #if defined(CONFIG_MACB) | |
ab0df36f HS |
60 | portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); |
61 | portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); | |
6b443944 HS |
62 | #endif |
63 | #if defined(CONFIG_MMC) | |
ab0df36f | 64 | portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); |
6b443944 | 65 | #endif |
5f723a3b | 66 | #if defined(CONFIG_ATMEL_SPI) |
ab0df36f | 67 | portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW); |
5f723a3b | 68 | #endif |
6b443944 HS |
69 | |
70 | return 0; | |
71 | } | |
72 | ||
25e6854d | 73 | int board_early_init_r(void) |
6b443944 HS |
74 | { |
75 | gd->bd->bi_phy_id[0] = 0x01; | |
76 | gd->bd->bi_phy_id[1] = 0x03; | |
25e6854d | 77 | return 0; |
6b443944 | 78 | } |
5f723a3b | 79 | |
c8c845cf BW |
80 | #ifdef CONFIG_CMD_NET |
81 | int board_eth_init(bd_t *bi) | |
82 | { | |
f4278b71 AB |
83 | macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); |
84 | macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); | |
c8c845cf BW |
85 | return 0; |
86 | } | |
87 | #endif | |
88 | ||
5f723a3b HS |
89 | /* SPI chip select control */ |
90 | #ifdef CONFIG_ATMEL_SPI | |
91 | #include <spi.h> | |
92 | ||
ab0df36f | 93 | #define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3) |
5f723a3b HS |
94 | |
95 | int spi_cs_is_valid(unsigned int bus, unsigned int cs) | |
96 | { | |
97 | return bus == 0 && cs == 0; | |
98 | } | |
99 | ||
100 | void spi_cs_activate(struct spi_slave *slave) | |
101 | { | |
102 | gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0); | |
103 | } | |
104 | ||
105 | void spi_cs_deactivate(struct spi_slave *slave) | |
106 | { | |
107 | gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1); | |
108 | } | |
109 | #endif /* CONFIG_ATMEL_SPI */ |