[thirdparty/u-boot.git] / board / atmel / atngw100 / atngw100.c

/*
 * Copyright (C) 2006 Atmel Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>

#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
	{
		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
		.phys		= (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
					| MMU_VMR_CACHE_NONE,
	}, {
		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
		.nr_pages	= EBI_SDRAM_SIZE >> PAGE_SHIFT,
		.phys		= (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
					| MMU_VMR_CACHE_WRBACK,
	},
};

static const struct sdram_config sdram_config = {
	.data_bits	= SDRAM_DATA_16BIT,
	.row_bits	= 13,
	.col_bits	= 9,
	.bank_bits	= 2,
	.cas		= 3,
	.twr		= 2,
	.trc		= 7,
	.trp		= 2,
	.trcd		= 2,
	.tras		= 5,
	.txsr		= 5,
	/* 7.81 us */
	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
};

int board_early_init_f(void)
{
	/* Enable SDRAM in the EBI mux */
	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));

	portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
	portmux_enable_usart1(PORTMUX_DRIVE_MIN);

#if defined(CONFIG_MACB)
	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
#if defined(CONFIG_ATMEL_SPI)
	portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
#endif

	return 0;
}

phys_size_t initdram(int board_type)
{
	unsigned long expected_size;
	unsigned long actual_size;
	void *sdram_base;

	sdram_base = uncached(EBI_SDRAM_BASE);

	expected_size = sdram_init(sdram_base, &sdram_config);
	actual_size = get_ram_size(sdram_base, expected_size);

	if (expected_size != actual_size)
		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
				actual_size >> 20, expected_size >> 20);

	return actual_size;
}

int board_early_init_r(void)
{
	gd->bd->bi_phy_id[0] = 0x01;
	gd->bd->bi_phy_id[1] = 0x03;
	return 0;
}

#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bi)
{
	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
	return 0;
}
#endif

/* SPI chip select control */
#ifdef CONFIG_ATMEL_SPI
#include <spi.h>

#define ATNGW100_DATAFLASH_CS_PIN	GPIO_PIN_PA(3)

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && cs == 0;
}

void spi_cs_activate(struct spi_slave *slave)
{
	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
}
#endif /* CONFIG_ATMEL_SPI */
Commit	Line	Data
6b443944 HS	1	/*
	2	* Copyright (C) 2006 Atmel Corporation
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
6b443944 HS	5	*/
	6	#include <common.h>
	7
	8	#include <asm/io.h>
	9	#include <asm/sdram.h>
d38da537	10	#include <asm/arch/clk.h>
6b443944	11	#include <asm/arch/gpio.h>
44453b25	12	#include <asm/arch/hmatrix.h>
1f36f73f	13	#include <asm/arch/mmu.h>
ab0df36f	14	#include <asm/arch/portmux.h>
89973f8a	15	#include <netdev.h>
6b443944 HS	16
	17	DECLARE_GLOBAL_DATA_PTR;
	18
1f36f73f HS	19	struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
	20	{
	21	.virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
	22	.nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
	23	.phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
	24	\| MMU_VMR_CACHE_NONE,
	25	}, {
	26	.virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
	27	.nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
	28	.phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
	29	\| MMU_VMR_CACHE_WRBACK,
	30	},
	31	};
	32
a23e277c HS	33	static const struct sdram_config sdram_config = {
a23e277c HS	34	.data_bits = SDRAM_DATA_16BIT,
6b443944 HS	35	.row_bits = 13,
	36	.col_bits = 9,
	37	.bank_bits = 2,
	38	.cas = 3,
	39	.twr = 2,
	40	.trc = 7,
	41	.trp = 2,
	42	.trcd = 2,
	43	.tras = 5,
	44	.txsr = 5,
d38da537 HS	45	/* 7.81 us */
d38da537 HS	46	.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
6b443944 HS	47	};
	48
	49	int board_early_init_f(void)
	50	{
44453b25 HS	51	/* Enable SDRAM in the EBI mux */
44453b25 HS	52	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
6b443944	53
ab0df36f HS	54	portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
ab0df36f HS	55	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
6b443944 HS	56
6b443944 HS	57	#if defined(CONFIG_MACB)
ab0df36f HS	58	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
ab0df36f HS	59	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
6b443944 HS	60	#endif
6b443944 HS	61	#if defined(CONFIG_MMC)
ab0df36f	62	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
6b443944	63	#endif
5f723a3b	64	#if defined(CONFIG_ATMEL_SPI)
ab0df36f	65	portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
5f723a3b	66	#endif
6b443944 HS	67
	68	return 0;
	69	}
	70
9973e3c6	71	phys_size_t initdram(int board_type)
6b443944	72	{
a23e277c HS	73	unsigned long expected_size;
	74	unsigned long actual_size;
	75	void *sdram_base;
	76
9cec2fc2	77	sdram_base = uncached(EBI_SDRAM_BASE);
a23e277c HS	78
	79	expected_size = sdram_init(sdram_base, &sdram_config);
	80	actual_size = get_ram_size(sdram_base, expected_size);
	81
a23e277c	82	if (expected_size != actual_size)
7f4b009f	83	printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
a23e277c HS	84	actual_size >> 20, expected_size >> 20);
	85
	86	return actual_size;
6b443944 HS	87	}
6b443944 HS	88
25e6854d	89	int board_early_init_r(void)
6b443944 HS	90	{
	91	gd->bd->bi_phy_id[0] = 0x01;
	92	gd->bd->bi_phy_id[1] = 0x03;
25e6854d	93	return 0;
6b443944	94	}
5f723a3b	95
c8c845cf BW	96	#ifdef CONFIG_CMD_NET
	97	int board_eth_init(bd_t *bi)
	98	{
f4278b71 AB	99	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
f4278b71 AB	100	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
c8c845cf BW	101	return 0;
	102	}
	103	#endif
	104
5f723a3b HS	105	/* SPI chip select control */
	106	#ifdef CONFIG_ATMEL_SPI
	107	#include <spi.h>
	108
ab0df36f	109	#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
5f723a3b HS	110
	111	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	112	{
	113	return bus == 0 && cs == 0;
	114	}
	115
	116	void spi_cs_activate(struct spi_slave *slave)
	117	{
	118	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
	119	}
	120
	121	void spi_cs_deactivate(struct spi_slave *slave)
	122	{
	123	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
	124	}
	125	#endif /* CONFIG_ATMEL_SPI */