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a420dfe2 AB |
1 | /* |
2 | * Copyright (C) 2010 Atmel Corporation | |
3 | * | |
4 | * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
a420dfe2 AB |
7 | */ |
8 | #include <common.h> | |
9 | ||
10 | #include <spi.h> | |
11 | #include <netdev.h> | |
12 | ||
13 | #include <asm/io.h> | |
14 | #include <asm/sdram.h> | |
15 | #include <asm/arch/clk.h> | |
16 | #include <asm/arch/gpio.h> | |
17 | #include <asm/arch/hmatrix.h> | |
18 | #include <asm/arch/mmu.h> | |
19 | #include <asm/arch/portmux.h> | |
20 | ||
21 | DECLARE_GLOBAL_DATA_PTR; | |
22 | ||
23 | struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { | |
24 | { | |
25 | /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */ | |
e9ed41cc AB |
26 | .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, |
27 | .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, | |
28 | .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) | |
a420dfe2 AB |
29 | | MMU_VMR_CACHE_NONE, |
30 | }, { | |
31 | /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */ | |
e9ed41cc AB |
32 | .virt_pgno = EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT, |
33 | .nr_pages = EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT, | |
34 | .phys = (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT) | |
a420dfe2 AB |
35 | | MMU_VMR_CACHE_NONE, |
36 | }, { | |
37 | /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */ | |
e9ed41cc AB |
38 | .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, |
39 | .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, | |
40 | .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) | |
a420dfe2 AB |
41 | | MMU_VMR_CACHE_WRBACK, |
42 | }, | |
43 | }; | |
44 | ||
45 | static const struct sdram_config sdram_config = { | |
46 | .data_bits = SDRAM_DATA_32BIT, | |
47 | .row_bits = 13, | |
48 | .col_bits = 10, | |
49 | .bank_bits = 2, | |
50 | .cas = 3, | |
51 | .twr = 2, | |
52 | .trc = 7, | |
53 | .trp = 2, | |
54 | .trcd = 2, | |
55 | .tras = 5, | |
56 | .txsr = 6, | |
57 | /* 7.81 us */ | |
58 | .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, | |
59 | }; | |
60 | ||
61 | int board_early_init_f(void) | |
62 | { | |
63 | /* Enable SDRAM in the EBI mux */ | |
64 | hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE) | |
65 | | HMATRIX_BIT(EBI_NAND_ENABLE)); | |
66 | ||
67 | portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND, | |
68 | PORTMUX_DRIVE_HIGH); | |
69 | portmux_select_gpio(PORTMUX_PORT_E, 1 << 23, | |
70 | PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH | |
71 | | PORTMUX_DRIVE_MIN); | |
18667860 AB |
72 | |
73 | sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); | |
74 | ||
a420dfe2 AB |
75 | portmux_enable_usart1(PORTMUX_DRIVE_MIN); |
76 | ||
77 | #if defined(CONFIG_MACB) | |
78 | portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); | |
79 | portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); | |
80 | #endif | |
81 | #if defined(CONFIG_MMC) | |
82 | portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); | |
83 | #endif | |
84 | #if defined(CONFIG_ATMEL_SPI) | |
85 | portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW); | |
86 | #endif | |
87 | ||
88 | return 0; | |
89 | } | |
90 | ||
a420dfe2 AB |
91 | int board_early_init_r(void) |
92 | { | |
93 | gd->bd->bi_phy_id[0] = 0x01; | |
94 | gd->bd->bi_phy_id[1] = 0x03; | |
95 | return 0; | |
96 | } | |
97 | ||
98 | #ifdef CONFIG_CMD_NET | |
99 | int board_eth_init(bd_t *bi) | |
100 | { | |
101 | macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]); | |
102 | macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]); | |
103 | return 0; | |
104 | } | |
105 | #endif | |
106 | ||
107 | /* SPI chip select control */ | |
108 | #ifdef CONFIG_ATMEL_SPI | |
109 | #define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3) | |
110 | ||
111 | int spi_cs_is_valid(unsigned int bus, unsigned int cs) | |
112 | { | |
113 | return bus == 0 && cs == 0; | |
114 | } | |
115 | ||
116 | void spi_cs_activate(struct spi_slave *slave) | |
117 | { | |
118 | gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0); | |
119 | } | |
120 | ||
121 | void spi_cs_deactivate(struct spi_slave *slave) | |
122 | { | |
123 | gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1); | |
124 | } | |
125 | #endif /* CONFIG_ATMEL_SPI */ |