[people/ms/u-boot.git] / board / atmel / sama5d2_ptc / sama5d2_ptc.c

/*
 * Copyright (C) 2016 Atmel
 *		      Wenyou.Yang <wenyou.yang@atmel.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <atmel_hlcdc.h>
#include <lcd.h>
#include <mmc.h>
#include <net.h>
#include <netdev.h>
#include <spi.h>
#include <version.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_usba_udc.h>
#include <asm/arch/atmel_sdhci.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sama5_sfr.h>
#include <asm/arch/sama5d2.h>
#include <asm/arch/sama5d3_smc.h>

DECLARE_GLOBAL_DATA_PTR;

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && cs == 0;
}

void spi_cs_activate(struct spi_slave *slave)
{
	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
}

static void board_spi0_hw_init(void)
{
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);

	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);

	at91_periph_clk_enable(ATMEL_ID_SPI0);
}

static void board_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;

	at91_periph_clk_enable(ATMEL_ID_HSMC);

	writel(AT91_SFR_EBICFG_DRIVE0_HIGH |
	       AT91_SFR_EBICFG_PULL0_NONE |
	       AT91_SFR_EBICFG_DRIVE1_HIGH |
	       AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);

	/* Configure SMC CS3 for NAND */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
	       &smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
	       AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
	       &smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
	       &smc->cs[3].cycle);
	writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
	       AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
	       AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3) |
	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
	       AT91_SMC_MODE_EXNW_DISABLE |
	       AT91_SMC_MODE_DBW_8 |
	       AT91_SMC_MODE_TDF_CYCLE(3),
	       &smc->cs[3].mode);

	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0);	/* D0 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0);	/* D1 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0);	/* D2 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0);	/* D3 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0);	/* D4 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0);	/* D5 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0);	/* D6 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0);	/* D7 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0);	/* RE */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0);	/* WE */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1);	/* NCS */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1);	/* RDY */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1);	/* ALE */
	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1);	/* CLE */
}

static void board_usb_hw_init(void)
{
	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
}

static void board_gmac_hw_init(void)
{
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0);	/* GTXCK */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0);	/* GTXEN */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0);	/* GRXDV */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0);	/* GRXER */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0);	/* GRX0 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0);	/* GRX1 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0);	/* GTX0 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0);	/* GTX1 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0);	/* GMDC */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0);	/* GMDIO */

	at91_periph_clk_enable(ATMEL_ID_GMAC);
}

static void board_uart0_hw_init(void)
{
	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1);	/* URXD0 */
	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0);	/* UTXD0 */

	at91_periph_clk_enable(CONFIG_USART_ID);
}

int board_early_init_f(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOC);
	at91_periph_clk_enable(ATMEL_ID_PIOD);

	board_uart0_hw_init();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_ATMEL_SPI
	board_spi0_hw_init();
#endif
#ifdef CONFIG_NAND_ATMEL
	board_nand_hw_init();
#endif
#ifdef CONFIG_MACB
	board_gmac_hw_init();
#endif
#ifdef CONFIG_CMD_USB
	board_usb_hw_init();
#endif
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	at91_udp_hw_init();
#endif

	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);
	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;

#ifdef CONFIG_MACB
	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
	if (rc)
		printf("GMAC register failed\n");
#endif

#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	usba_udc_probe(&pdata);
#ifdef CONFIG_USB_ETH_RNDIS
	usb_eth_initialize(bis);
#endif
#endif

	return rc;
}

/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#ifdef CONFIG_SPI_BOOT
	board_spi0_hw_init();
#endif

#ifdef CONFIG_NAND_BOOT
	board_nand_hw_init();
#endif
}

static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
{
	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);

	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
		    ATMEL_MPDDRC_CR_NR_ROW_14 |
		    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
		    ATMEL_MPDDRC_CR_DIC_DS |
		    ATMEL_MPDDRC_CR_DIS_DLL |
		    ATMEL_MPDDRC_CR_NB_8BANKS |
		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);

	ddrc->rtr = 0x511;

	ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
		      (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
		      (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
		      (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
		      (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
		      (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
		      (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
		      (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));

	ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
		      (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
		      (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
		      (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));

	ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
		      (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
		      (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
		      (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
		      (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
}

void mem_init(void)
{
	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
	struct atmel_mpddrc_config ddrc_config;
	u32 reg;

	ddrc_conf(&ddrc_config);

	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
	at91_system_clk_enable(AT91_PMC_DDR);

	reg = readl(&mpddrc->io_calibr);
	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
	writel(reg, &mpddrc->io_calibr);

	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
	       &mpddrc->rd_data_path);

	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);

	writel(0x3, &mpddrc->cal_mr4);
	writel(64, &mpddrc->tim_cal);
}

void at91_pmc_init(void)
{
	at91_plla_init(AT91_PMC_PLLAR_29 |
		       AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
		       AT91_PMC_PLLXR_MUL(82) |
		       AT91_PMC_PLLXR_DIV(1));

	at91_pllicpr_init(0);

	at91_mck_init(AT91_PMC_MCKR_H32MXDIV |
		      AT91_PMC_MCKR_PLLADIV_2 |
		      AT91_PMC_MCKR_MDIV_3 |
		      AT91_PMC_MCKR_CSS_PLLA);
}
#endif
Commit	Line	Data
9989c156 WY	1	/*
	2	* Copyright (C) 2016 Atmel
	3	* Wenyou.Yang <wenyou.yang@atmel.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <atmel_hlcdc.h>
	10	#include <lcd.h>
	11	#include <mmc.h>
	12	#include <net.h>
	13	#include <netdev.h>
	14	#include <spi.h>
	15	#include <version.h>
	16	#include <asm/io.h>
	17	#include <asm/arch/at91_common.h>
	18	#include <asm/arch/atmel_pio4.h>
	19	#include <asm/arch/atmel_mpddrc.h>
	20	#include <asm/arch/atmel_usba_udc.h>
	21	#include <asm/arch/atmel_sdhci.h>
	22	#include <asm/arch/clk.h>
	23	#include <asm/arch/gpio.h>
	24	#include <asm/arch/sama5_sfr.h>
	25	#include <asm/arch/sama5d2.h>
	26	#include <asm/arch/sama5d3_smc.h>
	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
	30	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	31	{
	32	return bus == 0 && cs == 0;
	33	}
	34
	35	void spi_cs_activate(struct spi_slave *slave)
	36	{
	37	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
	38	}
	39
	40	void spi_cs_deactivate(struct spi_slave *slave)
	41	{
	42	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
	43	}
	44
	45	static void board_spi0_hw_init(void)
	46	{
	47	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
	48	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
	49	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
	50
	51	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
	52
	53	at91_periph_clk_enable(ATMEL_ID_SPI0);
	54	}
	55
	56	static void board_nand_hw_init(void)
	57	{
	58	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	59	struct atmel_sfr sfr = (struct atmel_sfr )ATMEL_BASE_SFR;
	60
	61	at91_periph_clk_enable(ATMEL_ID_HSMC);
	62
	63	writel(AT91_SFR_EBICFG_DRIVE0_HIGH \|
	64	AT91_SFR_EBICFG_PULL0_NONE \|
65	AT91_SFR_EBICFG_DRIVE1_HIGH \|
66	AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);
67
68	/* Configure SMC CS3 for NAND */
69	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(1) \|
70	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(1),
71	&smc->cs[3].setup);
72	writel(AT91_SMC_PULSE_NWE(2) \| AT91_SMC_PULSE_NCS_WR(3) \|
73	AT91_SMC_PULSE_NRD(2) \| AT91_SMC_PULSE_NCS_RD(3),
74	&smc->cs[3].pulse);
75	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
76	&smc->cs[3].cycle);
77	writel(AT91_SMC_TIMINGS_TCLR(2) \| AT91_SMC_TIMINGS_TADL(7) \|
78	AT91_SMC_TIMINGS_TAR(2) \| AT91_SMC_TIMINGS_TRR(3) \|
79	AT91_SMC_TIMINGS_TWB(7) \| AT91_SMC_TIMINGS_RBNSEL(3) \|
80	AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
81	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
82	AT91_SMC_MODE_EXNW_DISABLE \|
83	AT91_SMC_MODE_DBW_8 \|
84	AT91_SMC_MODE_TDF_CYCLE(3),
85	&smc->cs[3].mode);
86
87	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0); /* D0 */
88	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0); /* D1 */
89	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0); /* D2 */
90	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0); /* D3 */
91	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0); /* D4 */
92	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0); /* D5 */
93	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0); /* D6 */
94	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0); /* D7 */
95	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0); /* RE */
96	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0); /* WE */
97	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1); /* NCS */
98	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1); /* RDY */
99	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1); /* ALE */
100	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1); /* CLE */
101	}
102
103	static void board_usb_hw_init(void)
104	{
105	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
106	}
107
108	static void board_gmac_hw_init(void)
109	{
110	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */
111	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */
112	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */
113	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */
114	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */
115	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */
116	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */
117	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */
118	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */
119	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */
120
121	at91_periph_clk_enable(ATMEL_ID_GMAC);
122	}
123
124	static void board_uart0_hw_init(void)
125	{
126	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1); /* URXD0 */
127	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
128
129	at91_periph_clk_enable(CONFIG_USART_ID);
130	}
131
132	int board_early_init_f(void)
133	{
134	at91_periph_clk_enable(ATMEL_ID_PIOA);
135	at91_periph_clk_enable(ATMEL_ID_PIOB);
136	at91_periph_clk_enable(ATMEL_ID_PIOC);
137	at91_periph_clk_enable(ATMEL_ID_PIOD);
138
139	board_uart0_hw_init();
140
141	return 0;
142	}
143
144	int board_init(void)
145	{
146	/* address of boot parameters */
147	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
148
149	#ifdef CONFIG_ATMEL_SPI
150	board_spi0_hw_init();
151	#endif
152	#ifdef CONFIG_NAND_ATMEL
153	board_nand_hw_init();
154	#endif
155	#ifdef CONFIG_MACB
156	board_gmac_hw_init();
157	#endif
158	#ifdef CONFIG_CMD_USB
159	board_usb_hw_init();
160	#endif
161	#ifdef CONFIG_USB_GADGET_ATMEL_USBA
162	at91_udp_hw_init();
163	#endif
164
165	return 0;
166	}
167
168	int dram_init(void)
169	{
170	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
171	CONFIG_SYS_SDRAM_SIZE);
172	return 0;
173	}
174
175	int board_eth_init(bd_t *bis)
176	{
177	int rc = 0;
178
179	#ifdef CONFIG_MACB
180	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
181	if (rc)
182	printf("GMAC register failed\n");
183	#endif
184
185	#ifdef CONFIG_USB_GADGET_ATMEL_USBA
186	usba_udc_probe(&pdata);
187	#ifdef CONFIG_USB_ETH_RNDIS
188	usb_eth_initialize(bis);
189	#endif
190	#endif
191
192	return rc;
193	}
194
195	/* SPL */
196	#ifdef CONFIG_SPL_BUILD
197	void spl_board_init(void)
198	{
5541543f	199	#ifdef CONFIG_SPI_BOOT
9989c156 WY	200	board_spi0_hw_init();
	201	#endif
	202
5541543f	203	#ifdef CONFIG_NAND_BOOT
9989c156 WY	204	board_nand_hw_init();
	205	#endif
	206	}
	207
	208	static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
	209	{
	210	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS \| ATMEL_MPDDRC_MD_DDR3_SDRAM);
	211
	212	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 \|
	213	ATMEL_MPDDRC_CR_NR_ROW_14 \|
	214	ATMEL_MPDDRC_CR_CAS_DDR_CAS5 \|
	215	ATMEL_MPDDRC_CR_DIC_DS \|
	216	ATMEL_MPDDRC_CR_DIS_DLL \|
	217	ATMEL_MPDDRC_CR_NB_8BANKS \|
	218	ATMEL_MPDDRC_CR_DECOD_INTERLEAVED \|
	219	ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
	220
	221	ddrc->rtr = 0x511;
	222
	223	ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) \|
	224	(3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) \|
	225	(4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) \|
	226	(9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) \|
	227	(3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) \|
	228	(4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) \|
	229	(4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) \|
	230	(4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
	231
	232	ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) \|
	233	(29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) \|
	234	(0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) \|
	235	(3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
	236
	237	ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) \|
	238	(0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) \|
	239	(0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) \|
	240	(4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) \|
	241	(7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
	242	}
	243
	244	void mem_init(void)
	245	{
	246	struct atmel_mpddr mpddrc = (struct atmel_mpddr )ATMEL_BASE_MPDDRC;
	247	struct atmel_mpddrc_config ddrc_config;
	248	u32 reg;
	249
	250	ddrc_conf(&ddrc_config);
	251
	252	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
	253	at91_system_clk_enable(AT91_PMC_DDR);
	254
	255	reg = readl(&mpddrc->io_calibr);
	256	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
	257	reg \|= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
	258	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
	259	reg \|= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
	260	writel(reg, &mpddrc->io_calibr);
	261
	262	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
	263	&mpddrc->rd_data_path);
	264
	265	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
	266
	267	writel(0x3, &mpddrc->cal_mr4);
268	writel(64, &mpddrc->tim_cal);
269	}
270
271	void at91_pmc_init(void)
272	{
273	at91_plla_init(AT91_PMC_PLLAR_29 \|
274	AT91_PMC_PLLXR_PLLCOUNT(0x3f) \|
275	AT91_PMC_PLLXR_MUL(82) \|
276	AT91_PMC_PLLXR_DIV(1));
277
278	at91_pllicpr_init(0);
279
280	at91_mck_init(AT91_PMC_MCKR_H32MXDIV \|
281	AT91_PMC_MCKR_PLLADIV_2 \|
282	AT91_PMC_MCKR_MDIV_3 \|
283	AT91_PMC_MCKR_CSS_PLLA);
284	}
285	#endif