[people/ms/u-boot.git] / board / atmel / sama5d2_xplained / sama5d2_xplained.c

/*
 * Copyright (C) 2015 Atmel Corporation
 *		      Wenyou.Yang <wenyou.yang@atmel.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <atmel_hlcdc.h>
#include <lcd.h>
#include <mmc.h>
#include <net.h>
#include <netdev.h>
#include <spi.h>
#include <version.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_usba_udc.h>
#include <asm/arch/atmel_sdhci.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sama5d2.h>

DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_DM_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && cs == 0;
}
#endif

void spi_cs_activate(struct spi_slave *slave)
{
	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
}

static void board_spi0_hw_init(void)
{
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);

	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);

	at91_periph_clk_enable(ATMEL_ID_SPI0);
}

static void board_usb_hw_init(void)
{
	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
}

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	.vl_col = 480,
	.vl_row = 272,
	.vl_clk = 9000000,
	.vl_bpix = LCD_BPP,
	.vl_tft = 1,
	.vl_hsync_len = 41,
	.vl_left_margin = 2,
	.vl_right_margin = 2,
	.vl_vsync_len = 11,
	.vl_upper_margin = 2,
	.vl_lower_margin = 2,
	.mmio = ATMEL_BASE_LCDC,
};

/* No power up/down pin for the LCD pannel */
void lcd_enable(void)	{ /* Empty! */ }
void lcd_disable(void)	{ /* Empty! */ }

unsigned int has_lcdc(void)
{
	return 1;
}

static void board_lcd_hw_init(void)
{
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0);	/* LCDPWM */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* LCDDISP */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0);	/* LCDVSYNC */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0);	/* LCDHSYNC */
	atmel_pio4_set_a_periph(AT91_PIO_PORTD,  0, 0);	/* LCDPCK */
	atmel_pio4_set_a_periph(AT91_PIO_PORTD,  1, 0);	/* LCDDEN */

	/* LCDDAT0 */
	/* LCDDAT1 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDDAT2 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDDAT3 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* LCDDAT4 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDDAT5 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDDAT6 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDDAT7 */

	/* LCDDAT8 */
	/* LCDDAT9 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDDAT10 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0);	/* LCDDAT11 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDDAT12 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDDAT13 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDDAT14 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDDAT15 */

	/* LCDD16 */
	/* LCDD17 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDDAT18 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDDAT19 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDAT20 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0);	/* LCDDAT21 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDDAT22 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDDAT23 */

	at91_periph_clk_enable(ATMEL_ID_LCDC);
}

#ifdef CONFIG_LCD_INFO
void lcd_show_board_info(void)
{
	ulong dram_size;
	int i;
	char temp[32];

	lcd_printf("%s\n", U_BOOT_VERSION);
	lcd_printf("2015 ATMEL Corp\n");
	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
		   strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	lcd_printf("%ld MB SDRAM\n", dram_size >> 20);
}
#endif /* CONFIG_LCD_INFO */
#endif /* CONFIG_LCD */

static void board_gmac_hw_init(void)
{
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0);	/* GTXCK */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0);	/* GTXEN */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0);	/* GRXDV */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0);	/* GRXER */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0);	/* GRX0 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0);	/* GRX1 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0);	/* GTX0 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0);	/* GTX1 */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0);	/* GMDC */
	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0);	/* GMDIO */

	at91_periph_clk_enable(ATMEL_ID_GMAC);
}

static void board_sdhci0_hw_init(void)
{
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* SDMMC0_CK */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* SDMMC0_CMD */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* SDMMC0_DAT0 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0);	/* SDMMC0_DAT1 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0);	/* SDMMC0_DAT2 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0);	/* SDMMC0_DAT3 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0);	/* SDMMC0_DAT4 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0);	/* SDMMC0_DAT5 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0);	/* SDMMC0_DAT6 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0);	/* SDMMC0_DAT7 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* SDMMC0_RSTN */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SDMMC0_VDDSEL */
	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SDMMC0_CD */

	at91_periph_clk_enable(ATMEL_ID_SDMMC0);
	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
					 GCK_CSS_UPLL_CLK, 1);
}

static void board_sdhci1_hw_init(void)
{
	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0);	/* SDMMC1_DAT0 */
	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0);	/* SDMMC1_DAT1 */
	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0);	/* SDMMC1_DAT2 */
	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0);	/* SDMMC1_DAT3 */
	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0);	/* SDMMC1_CK */
	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0);	/* SDMMC1_RSTN */
	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0);	/* SDMMC1_CMD */
	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0);	/* SDMMC1_CD */

	at91_periph_clk_enable(ATMEL_ID_SDMMC1);
	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
					 GCK_CSS_UPLL_CLK, 1);
}

int board_mmc_init(bd_t *bis)
{
#ifdef CONFIG_ATMEL_SDHCI0
	atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0);
#endif
#ifdef CONFIG_ATMEL_SDHCI1
	atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1);
#endif

	return 0;
}

static void board_uart1_hw_init(void)
{
	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* URXD1 */
	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);	/* UTXD1 */

	at91_periph_clk_enable(ATMEL_ID_UART1);
}

int board_early_init_f(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOC);
	at91_periph_clk_enable(ATMEL_ID_PIOD);

	board_uart1_hw_init();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_ATMEL_SPI
	board_spi0_hw_init();
#endif
#ifdef CONFIG_ATMEL_SDHCI
#ifdef CONFIG_ATMEL_SDHCI0
	board_sdhci0_hw_init();
#endif
#ifdef CONFIG_ATMEL_SDHCI1
	board_sdhci1_hw_init();
#endif
#endif
#ifdef CONFIG_MACB
	board_gmac_hw_init();
#endif
#ifdef CONFIG_LCD
	board_lcd_hw_init();
#endif
#ifdef CONFIG_CMD_USB
	board_usb_hw_init();
#endif
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	at91_udp_hw_init();
#endif

	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);
	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;

#ifdef CONFIG_MACB
	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
#endif

#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	usba_udc_probe(&pdata);
#ifdef CONFIG_USB_ETH_RNDIS
	usb_eth_initialize(bis);
#endif
#endif

	return rc;
}

/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#ifdef CONFIG_SYS_USE_SERIALFLASH
	board_spi0_hw_init();
#endif
#ifdef CONFIG_ATMEL_SDHCI
#ifdef CONFIG_ATMEL_SDHCI0
	board_sdhci0_hw_init();
#endif
#ifdef CONFIG_ATMEL_SDHCI1
	board_sdhci1_hw_init();
#endif
#endif
}

static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
{
	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);

	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
		    ATMEL_MPDDRC_CR_NR_ROW_14 |
		    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
		    ATMEL_MPDDRC_CR_DIC_DS |
		    ATMEL_MPDDRC_CR_DIS_DLL |
		    ATMEL_MPDDRC_CR_NB_8BANKS |
		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);

	ddrc->rtr = 0x511;

	ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
		      4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
		      9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
		      4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
		      4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
		      4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);

	ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
		      29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
		      0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
		      3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);

	ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
		      0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
		      4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
		      7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
}

void mem_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
	struct atmel_mpddrc_config ddrc_config;
	u32 reg;

	ddrc_conf(&ddrc_config);

	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
	writel(AT91_PMC_DDR, &pmc->scer);

	reg = readl(&mpddrc->io_calibr);
	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
	writel(reg, &mpddrc->io_calibr);

	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
	       &mpddrc->rd_data_path);

	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);

	writel(0x3, &mpddrc->cal_mr4);
	writel(64, &mpddrc->tim_cal);
}

void at91_pmc_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	u32 tmp;

	tmp = AT91_PMC_PLLAR_29 |
	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
	      AT91_PMC_PLLXR_MUL(82) |
	      AT91_PMC_PLLXR_DIV(1);
	at91_plla_init(tmp);

	writel(0x0 << 8, &pmc->pllicpr);

	tmp = AT91_PMC_MCKR_H32MXDIV |
	      AT91_PMC_MCKR_PLLADIV_2 |
	      AT91_PMC_MCKR_MDIV_3 |
	      AT91_PMC_MCKR_CSS_PLLA;
	at91_mck_init(tmp);
}
#endif
Commit	Line	Data
75238f23 WY	1	/*
	2	* Copyright (C) 2015 Atmel Corporation
	3	* Wenyou.Yang <wenyou.yang@atmel.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <atmel_hlcdc.h>
	10	#include <lcd.h>
	11	#include <mmc.h>
	12	#include <net.h>
	13	#include <netdev.h>
	14	#include <spi.h>
	15	#include <version.h>
	16	#include <asm/io.h>
	17	#include <asm/arch/at91_common.h>
75238f23	18	#include <asm/arch/atmel_pio4.h>
37dadbca	19	#include <asm/arch/atmel_mpddrc.h>
75238f23 WY	20	#include <asm/arch/atmel_usba_udc.h>
	21	#include <asm/arch/atmel_sdhci.h>
	22	#include <asm/arch/clk.h>
	23	#include <asm/arch/gpio.h>
	24	#include <asm/arch/sama5d2.h>
	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
6f170c4d	28	#ifndef CONFIG_DM_SPI
75238f23 WY	29	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	30	{
	31	return bus == 0 && cs == 0;
	32	}
6f170c4d	33	#endif
75238f23 WY	34
	35	void spi_cs_activate(struct spi_slave *slave)
	36	{
	37	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
	38	}
	39
	40	void spi_cs_deactivate(struct spi_slave *slave)
	41	{
	42	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
	43	}
	44
	45	static void board_spi0_hw_init(void)
	46	{
	47	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
	48	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
	49	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
	50
	51	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
	52
	53	at91_periph_clk_enable(ATMEL_ID_SPI0);
	54	}
	55
	56	static void board_usb_hw_init(void)
	57	{
	58	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
	59	}
	60
	61	#ifdef CONFIG_LCD
	62	vidinfo_t panel_info = {
	63	.vl_col = 480,
	64	.vl_row = 272,
	65	.vl_clk = 9000000,
	66	.vl_bpix = LCD_BPP,
	67	.vl_tft = 1,
	68	.vl_hsync_len = 41,
	69	.vl_left_margin = 2,
	70	.vl_right_margin = 2,
	71	.vl_vsync_len = 11,
	72	.vl_upper_margin = 2,
	73	.vl_lower_margin = 2,
	74	.mmio = ATMEL_BASE_LCDC,
	75	};
	76
	77	/* No power up/down pin for the LCD pannel */
	78	void lcd_enable(void) { /* Empty! */ }
	79	void lcd_disable(void) { /* Empty! */ }
	80
	81	unsigned int has_lcdc(void)
	82	{
	83	return 1;
	84	}
	85
	86	static void board_lcd_hw_init(void)
	87	{
	88	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */
	89	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */
	90	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */
	91	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */
	92	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */
	93	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */
	94
	95	/* LCDDAT0 */
	96	/* LCDDAT1 */
	97	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */
98	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */
99	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */
100	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */
101	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */
102	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */
103
104	/* LCDDAT8 */
105	/* LCDDAT9 */
106	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */
107	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */
108	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */
109	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */
110	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */
111	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */
112
113	/* LCDD16 */
114	/* LCDD17 */
115	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */
116	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */
117	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */
118	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */
119	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */
120	atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */
121
122	at91_periph_clk_enable(ATMEL_ID_LCDC);
123	}
124
125	#ifdef CONFIG_LCD_INFO
126	void lcd_show_board_info(void)
127	{
128	ulong dram_size;
129	int i;
130	char temp[32];
131
132	lcd_printf("%s\n", U_BOOT_VERSION);
133	lcd_printf("2015 ATMEL Corp\n");
134	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
135	strmhz(temp, get_cpu_clk_rate()));
136
137	dram_size = 0;
138	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
139	dram_size += gd->bd->bi_dram[i].size;
140
141	lcd_printf("%ld MB SDRAM\n", dram_size >> 20);
142	}
143	#endif /* CONFIG_LCD_INFO */
144	#endif /* CONFIG_LCD */
145
146	static void board_gmac_hw_init(void)
147	{
148	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0); /* GTXCK */
149	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0); /* GTXEN */
150	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0); /* GRXDV */
151	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0); /* GRXER */
152	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0); /* GRX0 */
153	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0); /* GRX1 */
154	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0); /* GTX0 */
155	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0); /* GTX1 */
156	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0); /* GMDC */
157	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0); /* GMDIO */
158
159	at91_periph_clk_enable(ATMEL_ID_GMAC);
160	}
161
162	static void board_sdhci0_hw_init(void)
163	{
164	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SDMMC0_CK */
165	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SDMMC0_CMD */
166	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SDMMC0_DAT0 */
167	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* SDMMC0_DAT1 */
168	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* SDMMC0_DAT2 */
169	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* SDMMC0_DAT3 */
170	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0); /* SDMMC0_DAT4 */
171	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0); /* SDMMC0_DAT5 */
172	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0); /* SDMMC0_DAT6 */
173	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0); /* SDMMC0_DAT7 */
174	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0); /* SDMMC0_RSTN */
175	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SDMMC0_VDDSEL */
a9c89bf1	176	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SDMMC0_CD */
75238f23 WY	177
	178	at91_periph_clk_enable(ATMEL_ID_SDMMC0);
	179	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
c043d8d8	180	GCK_CSS_UPLL_CLK, 1);
75238f23 WY	181	}
	182
	183	static void board_sdhci1_hw_init(void)
	184	{
	185	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0); /* SDMMC1_DAT0 */
	186	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0); /* SDMMC1_DAT1 */
	187	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0); /* SDMMC1_DAT2 */
	188	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0); /* SDMMC1_DAT3 */
	189	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0); /* SDMMC1_CK */
	190	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0); /* SDMMC1_RSTN */
	191	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0); /* SDMMC1_CMD */
	192	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0); /* SDMMC1_CD */
	193
	194	at91_periph_clk_enable(ATMEL_ID_SDMMC1);
	195	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
c043d8d8	196	GCK_CSS_UPLL_CLK, 1);
75238f23 WY	197	}
	198
	199	int board_mmc_init(bd_t *bis)
	200	{
	201	#ifdef CONFIG_ATMEL_SDHCI0
	202	atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0);
	203	#endif
	204	#ifdef CONFIG_ATMEL_SDHCI1
	205	atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1);
	206	#endif
	207
	208	return 0;
	209	}
	210
	211	static void board_uart1_hw_init(void)
	212	{
	213	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */
	214	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
	215
	216	at91_periph_clk_enable(ATMEL_ID_UART1);
	217	}
	218
	219	int board_early_init_f(void)
	220	{
	221	at91_periph_clk_enable(ATMEL_ID_PIOA);
	222	at91_periph_clk_enable(ATMEL_ID_PIOB);
	223	at91_periph_clk_enable(ATMEL_ID_PIOC);
	224	at91_periph_clk_enable(ATMEL_ID_PIOD);
	225
	226	board_uart1_hw_init();
	227
	228	return 0;
	229	}
	230
	231	int board_init(void)
	232	{
	233	/* address of boot parameters */
	234	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	235
	236	#ifdef CONFIG_ATMEL_SPI
	237	board_spi0_hw_init();
	238	#endif
	239	#ifdef CONFIG_ATMEL_SDHCI
	240	#ifdef CONFIG_ATMEL_SDHCI0
	241	board_sdhci0_hw_init();
	242	#endif
	243	#ifdef CONFIG_ATMEL_SDHCI1
	244	board_sdhci1_hw_init();
	245	#endif
	246	#endif
	247	#ifdef CONFIG_MACB
	248	board_gmac_hw_init();
	249	#endif
	250	#ifdef CONFIG_LCD
	251	board_lcd_hw_init();
	252	#endif
	253	#ifdef CONFIG_CMD_USB
	254	board_usb_hw_init();
	255	#endif
	256	#ifdef CONFIG_USB_GADGET_ATMEL_USBA
	257	at91_udp_hw_init();
	258	#endif
	259
	260	return 0;
261	}
262
263	int dram_init(void)
264	{
265	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
266	CONFIG_SYS_SDRAM_SIZE);
267	return 0;
268	}
269
270	int board_eth_init(bd_t *bis)
271	{
272	int rc = 0;
273
274	#ifdef CONFIG_MACB
275	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
276	#endif
277
278	#ifdef CONFIG_USB_GADGET_ATMEL_USBA
279	usba_udc_probe(&pdata);
280	#ifdef CONFIG_USB_ETH_RNDIS
281	usb_eth_initialize(bis);
282	#endif
283	#endif
284
285	return rc;
286	}
37dadbca WY	287
	288	/* SPL */
	289	#ifdef CONFIG_SPL_BUILD
	290	void spl_board_init(void)
	291	{
	292	#ifdef CONFIG_SYS_USE_SERIALFLASH
	293	board_spi0_hw_init();
	294	#endif
	295	#ifdef CONFIG_ATMEL_SDHCI
	296	#ifdef CONFIG_ATMEL_SDHCI0
	297	board_sdhci0_hw_init();
	298	#endif
	299	#ifdef CONFIG_ATMEL_SDHCI1
	300	board_sdhci1_hw_init();
	301	#endif
	302	#endif
	303	}
	304
	305	static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
	306	{
	307	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS \| ATMEL_MPDDRC_MD_DDR3_SDRAM);
	308
	309	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 \|
	310	ATMEL_MPDDRC_CR_NR_ROW_14 \|
	311	ATMEL_MPDDRC_CR_CAS_DDR_CAS5 \|
	312	ATMEL_MPDDRC_CR_DIC_DS \|
	313	ATMEL_MPDDRC_CR_DIS_DLL \|
	314	ATMEL_MPDDRC_CR_NB_8BANKS \|
	315	ATMEL_MPDDRC_CR_DECOD_INTERLEAVED \|
	316	ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
	317
	318	ddrc->rtr = 0x511;
	319
	320	ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET \|
	321	3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \|
	322	4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET \|
	323	9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET \|
	324	3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET \|
	325	4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET \|
	326	4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET \|
	327	4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
	328
	329	ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET \|
	330	29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET \|
	331	0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET \|
	332	3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);
	333
	334	ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET \|
	335	0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET \|
	336	0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET \|
	337	4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET \|
	338	7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
	339	}
	340
	341	void mem_init(void)
	342	{
	343	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	344	struct atmel_mpddr mpddrc = (struct atmel_mpddr )ATMEL_BASE_MPDDRC;
	345	struct atmel_mpddrc_config ddrc_config;
	346	u32 reg;
	347
	348	ddrc_conf(&ddrc_config);
	349
	350	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
351	writel(AT91_PMC_DDR, &pmc->scer);
352
353	reg = readl(&mpddrc->io_calibr);
354	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
355	reg \|= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
356	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
357	reg \|= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
358	writel(reg, &mpddrc->io_calibr);
359
360	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
361	&mpddrc->rd_data_path);
362
363	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
364
365	writel(0x3, &mpddrc->cal_mr4);
366	writel(64, &mpddrc->tim_cal);
367	}
368
369	void at91_pmc_init(void)
370	{
371	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
372	u32 tmp;
373
374	tmp = AT91_PMC_PLLAR_29 \|
375	AT91_PMC_PLLXR_PLLCOUNT(0x3f) \|
376	AT91_PMC_PLLXR_MUL(82) \|
377	AT91_PMC_PLLXR_DIV(1);
378	at91_plla_init(tmp);
379
380	writel(0x0 << 8, &pmc->pllicpr);
381
382	tmp = AT91_PMC_MCKR_H32MXDIV \|
383	AT91_PMC_MCKR_PLLADIV_2 \|
384	AT91_PMC_MCKR_MDIV_3 \|
385	AT91_PMC_MCKR_CSS_PLLA;
386	at91_mck_init(tmp);
387	}
388	#endif