[people/ms/u-boot.git] / board / atmel / sama5d3_xplained / sama5d3_xplained.c

/*
 * Copyright (C) 2014 Atmel Corporation
 *		      Bo Shen <voice.shen@atmel.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <atmel_mci.h>
#include <net.h>
#include <netdev.h>
#include <spl.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/at91_wdt.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_NAND_ATMEL
void sama5d3_xplained_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;

	at91_periph_clk_enable(ATMEL_ID_SMC);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
	       &smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
	       &smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
	       &smc->cs[3].cycle);
	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
	       AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
	       AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
	       AT91_SMC_MODE_DBW_8 |
#endif
	       AT91_SMC_MODE_TDF_CYCLE(3),
	       &smc->cs[3].mode);
}
#endif

#ifdef CONFIG_CMD_USB
static void sama5d3_xplained_usb_hw_init(void)
{
	at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
	at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
}
#endif

#ifdef CONFIG_GENERIC_ATMEL_MCI
static void sama5d3_xplained_mci0_hw_init(void)
{
	at91_mci_hw_init();

	at91_set_pio_output(AT91_PIO_PORTE, 2, 0);	/* MCI0 Power */
}
#endif

int board_early_init_f(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOC);
	at91_periph_clk_enable(ATMEL_ID_PIOD);
	at91_periph_clk_enable(ATMEL_ID_PIOE);

	at91_seriald_hw_init();

	return 0;
}

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_NAND_ATMEL
	sama5d3_xplained_nand_hw_init();
#endif
#ifdef CONFIG_CMD_USB
	sama5d3_xplained_usb_hw_init();
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
	sama5d3_xplained_mci0_hw_init();
#endif
#ifdef CONFIG_MACB
	at91_gmac_hw_init();
	at91_macb_hw_init();
#endif
	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);

	return 0;
}

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_MACB
	macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
	macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
#endif
	return 0;
}

#ifdef CONFIG_GENERIC_ATMEL_MCI
int board_mmc_init(bd_t *bis)
{
	atmel_mci_init((void *)ATMEL_BASE_MCI0);

	return 0;
}
#endif

/* SPL */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
#ifdef CONFIG_SYS_USE_MMC
	sama5d3_xplained_mci0_hw_init();
#elif CONFIG_SYS_USE_NANDFLASH
	sama5d3_xplained_nand_hw_init();
#endif
}

static void ddr2_conf(struct atmel_mpddr *ddr2)
{
	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);

	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
		    ATMEL_MPDDRC_CR_NR_ROW_14 |
		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
		    ATMEL_MPDDRC_CR_ENRDM_ON |
		    ATMEL_MPDDRC_CR_NB_8BANKS |
		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
	/*
	 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
	 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
	 */
	ddr2->rtr = 0x411;

	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);

	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
		      28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
		      26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);

	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
		      2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}

void mem_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	struct atmel_mpddr ddr2;

	ddr2_conf(&ddr2);

	/* enable MPDDR clock */
	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
	writel(0x4, &pmc->scer);

	/* DDRAM2 Controller initialize */
	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
}

void at91_pmc_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	u32 tmp;

	tmp = AT91_PMC_PLLAR_29 |
	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
	      AT91_PMC_PLLXR_MUL(43) |
	      AT91_PMC_PLLXR_DIV(1);
	at91_plla_init(tmp);

	writel(0x3 << 8, &pmc->pllicpr);

	tmp = AT91_PMC_MCKR_MDIV_4 |
	      AT91_PMC_MCKR_CSS_PLLA;
	at91_mck_init(tmp);
}
#endif
Commit	Line	Data
7ca6f363 BS	1	/*
	2	* Copyright (C) 2014 Atmel Corporation
	3	* Bo Shen <voice.shen@atmel.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <mmc.h>
	10	#include <asm/io.h>
	11	#include <asm/arch/sama5d3_smc.h>
	12	#include <asm/arch/at91_common.h>
	13	#include <asm/arch/at91_pmc.h>
	14	#include <asm/arch/at91_rstc.h>
	15	#include <asm/arch/gpio.h>
	16	#include <asm/arch/clk.h>
	17	#include <atmel_mci.h>
	18	#include <net.h>
	19	#include <netdev.h>
cd23aac4 BS	20	#include <spl.h>
	21	#include <asm/arch/atmel_mpddrc.h>
	22	#include <asm/arch/at91_wdt.h>
7ca6f363 BS	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
	26	#ifdef CONFIG_NAND_ATMEL
	27	void sama5d3_xplained_nand_hw_init(void)
	28	{
	29	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	30
	31	at91_periph_clk_enable(ATMEL_ID_SMC);
	32
	33	/* Configure SMC CS3 for NAND/SmartMedia */
	34	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(1) \|
	35	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(1),
	36	&smc->cs[3].setup);
	37	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(5) \|
	38	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(5),
	39	&smc->cs[3].pulse);
	40	writel(AT91_SMC_CYCLE_NWE(8) \| AT91_SMC_CYCLE_NRD(8),
	41	&smc->cs[3].cycle);
	42	writel(AT91_SMC_TIMINGS_TCLR(3) \| AT91_SMC_TIMINGS_TADL(10) \|
	43	AT91_SMC_TIMINGS_TAR(3) \| AT91_SMC_TIMINGS_TRR(4) \|
	44	AT91_SMC_TIMINGS_TWB(5) \| AT91_SMC_TIMINGS_RBNSEL(3)\|
	45	AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
	46	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	47	AT91_SMC_MODE_EXNW_DISABLE \|
	48	#ifdef CONFIG_SYS_NAND_DBW_16
	49	AT91_SMC_MODE_DBW_16 \|
	50	#else /* CONFIG_SYS_NAND_DBW_8 */
	51	AT91_SMC_MODE_DBW_8 \|
	52	#endif
	53	AT91_SMC_MODE_TDF_CYCLE(3),
	54	&smc->cs[3].mode);
	55	}
	56	#endif
	57
	58	#ifdef CONFIG_CMD_USB
	59	static void sama5d3_xplained_usb_hw_init(void)
	60	{
	61	at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
	62	at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
	63	}
	64	#endif
	65
	66	#ifdef CONFIG_GENERIC_ATMEL_MCI
	67	static void sama5d3_xplained_mci0_hw_init(void)
	68	{
	69	at91_mci_hw_init();
	70
	71	at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */
	72	}
	73	#endif
	74
	75	int board_early_init_f(void)
	76	{
	77	at91_periph_clk_enable(ATMEL_ID_PIOA);
	78	at91_periph_clk_enable(ATMEL_ID_PIOB);
	79	at91_periph_clk_enable(ATMEL_ID_PIOC);
	80	at91_periph_clk_enable(ATMEL_ID_PIOD);
	81	at91_periph_clk_enable(ATMEL_ID_PIOE);
	82
	83	at91_seriald_hw_init();
	84
	85	return 0;
	86	}
87
88	int board_init(void)
89	{
90	/* adress of boot parameters */
91	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
92
93	#ifdef CONFIG_NAND_ATMEL
94	sama5d3_xplained_nand_hw_init();
95	#endif
96	#ifdef CONFIG_CMD_USB
97	sama5d3_xplained_usb_hw_init();
98	#endif
99	#ifdef CONFIG_GENERIC_ATMEL_MCI
100	sama5d3_xplained_mci0_hw_init();
101	#endif
102	#ifdef CONFIG_MACB
103	at91_gmac_hw_init();
104	at91_macb_hw_init();
105	#endif
106	return 0;
107	}
108
109	int dram_init(void)
110	{
111	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
112	CONFIG_SYS_SDRAM_SIZE);
113
114	return 0;
115	}
116
117	int board_eth_init(bd_t *bis)
118	{
119	#ifdef CONFIG_MACB
120	macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
121	macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
122	#endif
123	return 0;
124	}
125
126	#ifdef CONFIG_GENERIC_ATMEL_MCI
127	int board_mmc_init(bd_t *bis)
128	{
129	atmel_mci_init((void *)ATMEL_BASE_MCI0);
130
131	return 0;
132	}
133	#endif
cd23aac4 BS	134
	135	/* SPL */
	136	#ifdef CONFIG_SPL_BUILD
	137	void spl_board_init(void)
	138	{
	139	#ifdef CONFIG_SYS_USE_MMC
	140	sama5d3_xplained_mci0_hw_init();
	141	#elif CONFIG_SYS_USE_NANDFLASH
	142	sama5d3_xplained_nand_hw_init();
	143	#endif
	144	}
	145
	146	static void ddr2_conf(struct atmel_mpddr *ddr2)
	147	{
	148	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS \| ATMEL_MPDDRC_MD_DDR2_SDRAM);
	149
	150	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 \|
	151	ATMEL_MPDDRC_CR_NR_ROW_14 \|
	152	ATMEL_MPDDRC_CR_CAS_DDR_CAS3 \|
	153	ATMEL_MPDDRC_CR_ENRDM_ON \|
	154	ATMEL_MPDDRC_CR_NB_8BANKS \|
	155	ATMEL_MPDDRC_CR_NDQS_DISABLED \|
	156	ATMEL_MPDDRC_CR_DECOD_INTERLEAVED \|
	157	ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
	158	/*
	159	* As the DDR2-SDRAm device requires a refresh time is 7.8125us
	160	* when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
	161	*/
	162	ddr2->rtr = 0x411;
	163
	164	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET \|
	165	2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \|
	166	2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET \|
	167	8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET \|
	168	2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET \|
	169	2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET \|
	170	2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET \|
	171	2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
	172
	173	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET \|
	174	200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET \|
	175	28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET \|
	176	26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
	177
	178	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET \|
	179	2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET \|
	180	2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET \|
	181	7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET \|
	182	8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
	183	}
	184
	185	void mem_init(void)
	186	{
	187	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	188	struct atmel_mpddr ddr2;
	189
	190	ddr2_conf(&ddr2);
	191
	192	/* enable MPDDR clock */
	193	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
	194	writel(0x4, &pmc->scer);
	195
	196	/* DDRAM2 Controller initialize */
	197	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
198	}
199
200	void at91_pmc_init(void)
201	{
202	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
203	u32 tmp;
204
205	tmp = AT91_PMC_PLLAR_29 \|
206	AT91_PMC_PLLXR_PLLCOUNT(0x3f) \|
207	AT91_PMC_PLLXR_MUL(43) \|
208	AT91_PMC_PLLXR_DIV(1);
209	at91_plla_init(tmp);
210
211	writel(0x3 << 8, &pmc->pllicpr);
212
213	tmp = AT91_PMC_MCKR_MDIV_4 \|
214	AT91_PMC_MCKR_CSS_PLLA;
215	at91_mck_init(tmp);
216	}
217	#endif