[people/ms/u-boot.git] / board / atum8548 / atum8548.c

/*
 * Copyright 2007
 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
 *
 * Copyright 2007 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>

long int fixed_sdram(void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);

	if ((uint)&gur->porpllsr != 0xe00e0000) {
		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
	}
	printf ("Board: ATUM8548\n");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
	ecm->eeer = 0xffffffff;		/* Enable ecm errors */

	return 0;
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
long int fixed_sdram (void)
{
	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
    #if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000000D;
	ddr->err_sbe = 0x00ff0000;
    #endif
	asm("sync;isync;msync");
	udelay(500);
    #if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
    #else
	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
    #endif
	asm("sync; isync; msync");
	udelay(500);
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */

phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if defined(CONFIG_SPD_EEPROM)
	puts("fsl_ddr_sdram\n");
	dram_size = fsl_ddr_sdram();
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;
#else
	puts("fixed_sdram\n");
	dram_size = fixed_sdram ();
#endif

	puts("    DDR: ");
	return dram_size;
}

#if defined(CONFIG_SYS_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CONFIG_SYS_MEMTEST_START,
	       CONFIG_SYS_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++) {
		printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
		*p = 0xaaaaaaaa;
	}

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCI2
static struct pci_controller pci2_hose;
#endif

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

int first_free_busno=0;

void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
		devdisr, io_sel, host_agent);

	/* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
	gur->clkocr  |= MPC85xx_ATUM_CLKOCR;

	if (io_sel & 1) {
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
			printf ("    eTSEC1 is in sgmii mode.\n");
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
			printf ("    eTSEC2 is in sgmii mode.\n");
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
			printf ("    eTSEC3 is in sgmii mode.\n");
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
			printf ("    eTSEC4 is in sgmii mode.\n");
	}

#ifdef CONFIG_PCIE1
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
	struct pci_controller *hose = &pcie1_hose;
	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
	struct pci_region *r = hose->regions;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE1 connected to slot as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_MEM_BASE,
			       CONFIG_SYS_PCIE1_MEM_PHYS,
			       CONFIG_SYS_PCIE1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_IO_BASE,
			       CONFIG_SYS_PCIE1_IO_PHYS,
			       CONFIG_SYS_PCIE1_IO_SIZE,
			       PCI_REGION_IO);

#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCIE1_MEM_BASE2,
			       CONFIG_SYS_PCIE1_MEM_PHYS2,
			       CONFIG_SYS_PCIE1_MEM_SIZE2,
			       PCI_REGION_MEM);
#endif
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;

		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);

		first_free_busno=hose->last_busno+1;
		printf("    PCIE1 on bus %02x - %02x\n",
		       hose->first_busno,hose->last_busno);

	} else {
		printf ("    PCIE1: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif

#ifdef CONFIG_PCI1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
	struct pci_controller *hose = &pci1_hose;
	struct pci_region *r = hose->regions;

	uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
	uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		printf ("\n    PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			(uint)pci
			);

		/* outbound memory */
		pci_set_region(r++,
			       CONFIG_SYS_PCI1_MEM_BASE,
			       CONFIG_SYS_PCI1_MEM_PHYS,
			       CONFIG_SYS_PCI1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
			       CONFIG_SYS_PCI1_IO_BASE,
			       CONFIG_SYS_PCI1_IO_PHYS,
			       CONFIG_SYS_PCI1_IO_SIZE,
			       PCI_REGION_IO);
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;

		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
		first_free_busno=hose->last_busno+1;
		printf ("PCI1 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);
	} else {
		printf ("    PCI1: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif

#ifdef CONFIG_PCI2
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
	struct pci_controller *hose = &pci2_hose;
	struct pci_region *r = hose->regions;

	if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
		pci_set_region(r++,
			       CONFIG_SYS_PCI2_MEM_BASE,
			       CONFIG_SYS_PCI2_MEM_PHYS,
			       CONFIG_SYS_PCI2_MEM_SIZE,
			       PCI_REGION_MEM);

		pci_set_region(r++,
			       CONFIG_SYS_PCI2_IO_BASE,
			       CONFIG_SYS_PCI2_IO_PHYS,
			       CONFIG_SYS_PCI2_IO_SIZE,
			       PCI_REGION_IO);
		hose->region_count = r - hose->regions;
		hose->first_busno=first_free_busno;

		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
		first_free_busno=hose->last_busno+1;
		printf ("PCI2 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);
	} else {
		printf ("    PCI2: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI2;
#endif
}


int last_stage_init(void)
{
	int ic = icache_status ();
	printf ("icache_status: %d\n", ic);
	return 0;
}

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

#ifdef CONFIG_PCI1
	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
	ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
#ifdef CONFIG_PCIE1
	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
}
#endif
Commit	Line	Data
b964e936	1	/*
	2	* Copyright 2007
	3	* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
	4	*
	5	* Copyright 2007 Freescale Semiconductor, Inc.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <command.h>
	28	#include <pci.h>
	29	#include <asm/processor.h>
	30	#include <asm/immap_85xx.h>
c8514622	31	#include <asm/fsl_pci.h>
a947e4c7	32	#include <asm/fsl_ddr_sdram.h>
b964e936	33	#include <asm/io.h>
a947e4c7	34	#include <asm/mmu.h>
a30a549a	35	#include <spd_sdram.h>
b964e936	36	#include <miiphy.h>
	37	#include <libfdt.h>
	38	#include <fdt_support.h>
	39
b964e936	40	long int fixed_sdram(void);
	41
	42	int board_early_init_f (void)
	43	{
	44	return 0;
	45	}
	46
	47	int checkboard (void)
	48	{
6d0f6bcf JCPV	49	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	50	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
	51	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
b964e936	52
b964e936	53	if ((uint)&gur->porpllsr != 0xe00e0000) {
9b55a253	54	printf("immap size error %lx\n",(ulong)&gur->porpllsr);
b964e936	55	}
	56	printf ("Board: ATUM8548\n");
	57
	58	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	59	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
	60	ecm->eedr = 0xffffffff; /* Clear ecm errors */
	61	ecm->eeer = 0xffffffff; /* Enable ecm errors */
	62
	63	return 0;
	64	}
	65
	66	#if !defined(CONFIG_SPD_EEPROM)
	67	/*************************************************************************
	68	* fixed sdram init -- doesn't use serial presence detect.
	69	************************************************************************/
	70	long int fixed_sdram (void)
	71	{
6d0f6bcf JCPV	72	volatile ccsr_ddr_t ddr= (void )(CONFIG_SYS_MPC85xx_DDR_ADDR);
	73
	74	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	75	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	76	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	77	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	78	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	79	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	80	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
b964e936	81	#if defined (CONFIG_DDR_ECC)
	82	ddr->err_disable = 0x0000000D;
	83	ddr->err_sbe = 0x00ff0000;
	84	#endif
	85	asm("sync;isync;msync");
	86	udelay(500);
	87	#if defined (CONFIG_DDR_ECC)
	88	/* Enable ECC checking */
6d0f6bcf	89	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL \| 0x20000000);
b964e936	90	#else
6d0f6bcf	91	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
b964e936	92	#endif
	93	asm("sync; isync; msync");
	94	udelay(500);
6d0f6bcf	95	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
b964e936	96	}
	97	#endif /* !defined(CONFIG_SPD_EEPROM) */
	98
9973e3c6	99	phys_size_t
b964e936	100	initdram(int board_type)
	101	{
	102	long dram_size = 0;
	103
	104	puts("Initializing\n");
	105
	106	#if defined(CONFIG_SPD_EEPROM)
a947e4c7 KG	107	puts("fsl_ddr_sdram\n");
	108	dram_size = fsl_ddr_sdram();
	109	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	110	dram_size *= 0x100000;
b964e936	111	#else
	112	puts("fixed_sdram\n");
	113	dram_size = fixed_sdram ();
	114	#endif
	115
b964e936	116	puts(" DDR: ");
	117	return dram_size;
	118	}
	119
6d0f6bcf	120	#if defined(CONFIG_SYS_DRAM_TEST)
b964e936	121	int
	122	testdram(void)
	123	{
6d0f6bcf JCPV	124	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	125	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
b964e936	126	uint *p;
	127
	128	printf("Testing DRAM from 0x%08x to 0x%08x\n",
6d0f6bcf JCPV	129	CONFIG_SYS_MEMTEST_START,
6d0f6bcf JCPV	130	CONFIG_SYS_MEMTEST_END);
b964e936	131
	132	printf("DRAM test phase 1:\n");
	133	for (p = pstart; p < pend; p++) {
	134	printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
	135	*p = 0xaaaaaaaa;
d3a6532c	136	}
b964e936	137
	138	for (p = pstart; p < pend; p++) {
	139	if (*p != 0xaaaaaaaa) {
	140	printf ("DRAM test fails at: %08x\n", (uint) p);
	141	return 1;
	142	}
	143	}
	144
	145	printf("DRAM test phase 2:\n");
	146	for (p = pstart; p < pend; p++)
	147	*p = 0x55555555;
	148
	149	for (p = pstart; p < pend; p++) {
	150	if (*p != 0x55555555) {
	151	printf ("DRAM test fails at: %08x\n", (uint) p);
	152	return 1;
	153	}
	154	}
	155
	156	printf("DRAM test passed.\n");
	157	return 0;
	158	}
	159	#endif
	160
	161	#ifdef CONFIG_PCI1
	162	static struct pci_controller pci1_hose;
	163	#endif
	164
	165	#ifdef CONFIG_PCI2
	166	static struct pci_controller pci2_hose;
	167	#endif
	168
	169	#ifdef CONFIG_PCIE1
	170	static struct pci_controller pcie1_hose;
	171	#endif
	172
	173	int first_free_busno=0;
	174
	175	void
	176	pci_init_board(void)
	177	{
6d0f6bcf	178	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
b964e936	179
	180	uint devdisr = gur->devdisr;
	181	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	182	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	183
	184	debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
	185	devdisr, io_sel, host_agent);
	186
d3a6532c	187	/* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
b964e936	188	gur->clkocr \|= MPC85xx_ATUM_CLKOCR;
	189
	190	if (io_sel & 1) {
	191	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	192	printf (" eTSEC1 is in sgmii mode.\n");
	193	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
	194	printf (" eTSEC2 is in sgmii mode.\n");
	195	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	196	printf (" eTSEC3 is in sgmii mode.\n");
	197	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
	198	printf (" eTSEC4 is in sgmii mode.\n");
	199	}
	200
	201	#ifdef CONFIG_PCIE1
	202	{
6d0f6bcf	203	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE1_ADDR;
b964e936	204	struct pci_controller *hose = &pcie1_hose;
865f24dc KG	205	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
865f24dc KG	206	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
2dba0dea	207	struct pci_region *r = hose->regions;
b964e936	208
	209	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	210	printf ("\n PCIE1 connected to slot as %s (base address %x)",
	211	pcie_ep ? "End Point" : "Root Complex",
	212	(uint)pci);
	213	if (pci->pme_msg_det) {
	214	pci->pme_msg_det = 0xffffffff;
	215	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	216	}
	217	printf ("\n");
	218
b964e936	219	/* outbound memory */
2dba0dea	220	pci_set_region(r++,
6d0f6bcf JCPV	221	CONFIG_SYS_PCIE1_MEM_BASE,
	222	CONFIG_SYS_PCIE1_MEM_PHYS,
	223	CONFIG_SYS_PCIE1_MEM_SIZE,
b964e936	224	PCI_REGION_MEM);
	225
	226	/* outbound io */
2dba0dea	227	pci_set_region(r++,
6d0f6bcf JCPV	228	CONFIG_SYS_PCIE1_IO_BASE,
	229	CONFIG_SYS_PCIE1_IO_PHYS,
	230	CONFIG_SYS_PCIE1_IO_SIZE,
b964e936	231	PCI_REGION_IO);
b964e936	232
6d0f6bcf	233	#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
b964e936	234	/* outbound memory */
2dba0dea	235	pci_set_region(r++,
6d0f6bcf JCPV	236	CONFIG_SYS_PCIE1_MEM_BASE2,
	237	CONFIG_SYS_PCIE1_MEM_PHYS2,
	238	CONFIG_SYS_PCIE1_MEM_SIZE2,
b964e936	239	PCI_REGION_MEM);
b964e936	240	#endif
2dba0dea	241	hose->region_count = r - hose->regions;
b964e936	242	hose->first_busno=first_free_busno;
b964e936	243
fb3143b3	244	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
b964e936	245
	246	first_free_busno=hose->last_busno+1;
	247	printf(" PCIE1 on bus %02x - %02x\n",
	248	hose->first_busno,hose->last_busno);
	249
	250	} else {
	251	printf (" PCIE1: disabled\n");
	252	}
	253
	254	}
	255	#else
	256	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
	257	#endif
	258
	259	#ifdef CONFIG_PCI1
	260	{
6d0f6bcf	261	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI1_ADDR;
b964e936	262	struct pci_controller *hose = &pci1_hose;
2dba0dea	263	struct pci_region *r = hose->regions;
b964e936	264
865f24dc	265	uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
b964e936	266	uint pci_speed = 33333000; /get_clock_freq (); PCI PSPEED in [4:5] /
	267	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
	268	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
	269	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
	270
	271	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
	272	printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
	273	(pci_32) ? 32 : 64,
	274	(pci_speed == 33333000) ? "33" :
	275	(pci_speed == 66666000) ? "66" : "unknown",
	276	pci_clk_sel ? "sync" : "async",
	277	pci_agent ? "agent" : "host",
	278	pci_arb ? "arbiter" : "external-arbiter",
	279	(uint)pci
	280	);
	281
b964e936	282	/* outbound memory */
2dba0dea	283	pci_set_region(r++,
6d0f6bcf JCPV	284	CONFIG_SYS_PCI1_MEM_BASE,
	285	CONFIG_SYS_PCI1_MEM_PHYS,
	286	CONFIG_SYS_PCI1_MEM_SIZE,
b964e936	287	PCI_REGION_MEM);
	288
	289	/* outbound io */
2dba0dea	290	pci_set_region(r++,
6d0f6bcf JCPV	291	CONFIG_SYS_PCI1_IO_BASE,
	292	CONFIG_SYS_PCI1_IO_PHYS,
	293	CONFIG_SYS_PCI1_IO_SIZE,
b964e936	294	PCI_REGION_IO);
2dba0dea	295	hose->region_count = r - hose->regions;
b964e936	296	hose->first_busno=first_free_busno;
b964e936	297
fb3143b3	298	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
b964e936	299	first_free_busno=hose->last_busno+1;
	300	printf ("PCI1 on bus %02x - %02x\n",
	301	hose->first_busno,hose->last_busno);
	302	} else {
	303	printf (" PCI1: disabled\n");
	304	}
	305	}
	306	#else
	307	gur->devdisr \|= MPC85xx_DEVDISR_PCI1; /* disable */
	308	#endif
	309
	310	#ifdef CONFIG_PCI2
	311	{
6d0f6bcf	312	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI2_ADDR;
b964e936	313	struct pci_controller *hose = &pci2_hose;
2dba0dea	314	struct pci_region *r = hose->regions;
b964e936	315
b964e936	316	if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
2dba0dea	317	pci_set_region(r++,
6d0f6bcf JCPV	318	CONFIG_SYS_PCI2_MEM_BASE,
	319	CONFIG_SYS_PCI2_MEM_PHYS,
	320	CONFIG_SYS_PCI2_MEM_SIZE,
b964e936	321	PCI_REGION_MEM);
b964e936	322
2dba0dea	323	pci_set_region(r++,
6d0f6bcf JCPV	324	CONFIG_SYS_PCI2_IO_BASE,
	325	CONFIG_SYS_PCI2_IO_PHYS,
	326	CONFIG_SYS_PCI2_IO_SIZE,
b964e936	327	PCI_REGION_IO);
2dba0dea	328	hose->region_count = r - hose->regions;
b964e936	329	hose->first_busno=first_free_busno;
b964e936	330
fb3143b3	331	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
b964e936	332	first_free_busno=hose->last_busno+1;
	333	printf ("PCI2 on bus %02x - %02x\n",
	334	hose->first_busno,hose->last_busno);
	335	} else {
	336	printf (" PCI2: disabled\n");
	337	}
	338	}
	339	#else
	340	gur->devdisr \|= MPC85xx_DEVDISR_PCI2;
	341	#endif
	342	}
	343
	344
	345	int last_stage_init(void)
	346	{
d3a6532c	347	int ic = icache_status ();
b964e936	348	printf ("icache_status: %d\n", ic);
	349	return 0;
	350	}
	351
	352	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea	353	void ft_board_setup(void blob, bd_t bd)
b964e936	354	{
b964e936	355	ft_cpu_setup(blob, bd);
b964e936	356
b964e936	357	#ifdef CONFIG_PCI1
2dba0dea	358	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
b964e936	359	#endif
b964e936	360	#ifdef CONFIG_PCI2
2dba0dea	361	ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
b964e936	362	#endif
b964e936	363	#ifdef CONFIG_PCIE1
2dba0dea	364	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
b964e936	365	#endif
b964e936	366	}
b964e936	367	#endif