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5d6050fd SR |
1 | /* |
2 | * Copyright (C) 2014, Barco (www.barco.com) | |
3 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/gpio.h> | |
10 | #include <asm/io.h> | |
11 | #include <asm/arch/clock.h> | |
12 | #include <asm/arch/iomux.h> | |
13 | #include <asm/arch/mx6-pins.h> | |
552a848e SB |
14 | #include <asm/mach-imx/iomux-v3.h> |
15 | #include <asm/mach-imx/mxc_i2c.h> | |
5d6050fd SR |
16 | #include <i2c.h> |
17 | #include <miiphy.h> | |
18 | ||
19 | #include "platinum.h" | |
20 | ||
21 | #define GPIO_IP_NCONFIG IMX_GPIO_NR(5, 18) | |
22 | #define GPIO_HK_NCONFIG IMX_GPIO_NR(7, 13) | |
23 | #define GPIO_LS_NCONFIG IMX_GPIO_NR(5, 19) | |
24 | ||
25 | #define GPIO_I2C0_SEL0 IMX_GPIO_NR(5, 2) | |
26 | #define GPIO_I2C0_SEL1 IMX_GPIO_NR(1, 11) | |
27 | #define GPIO_I2C0_ENBN IMX_GPIO_NR(1, 13) | |
28 | ||
29 | #define GPIO_I2C2_SEL0 IMX_GPIO_NR(1, 17) | |
30 | #define GPIO_I2C2_SEL1 IMX_GPIO_NR(1, 20) | |
31 | #define GPIO_I2C2_ENBN IMX_GPIO_NR(1, 14) | |
32 | ||
33 | #define GPIO_USB_RESET IMX_GPIO_NR(1, 5) | |
34 | ||
35 | iomux_v3_cfg_t const ecspi1_pads[] = { | |
36 | MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), | |
37 | MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), | |
38 | MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), | |
39 | MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), | |
40 | MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), | |
41 | MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), | |
42 | }; | |
43 | ||
44 | iomux_v3_cfg_t const ecspi2_pads[] = { | |
45 | MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), | |
46 | MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), | |
47 | MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), | |
48 | MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), | |
49 | MX6_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(ECSPI_PAD_SS), | |
50 | }; | |
51 | ||
52 | iomux_v3_cfg_t const enet_pads[] = { | |
53 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
54 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
55 | MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
56 | MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
57 | MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
58 | MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
59 | MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
60 | MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
61 | MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
62 | MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
63 | }; | |
64 | ||
65 | /* PHY nRESET */ | |
66 | iomux_v3_cfg_t const phy_reset_pad = { | |
67 | MX6_PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
68 | }; | |
69 | ||
70 | iomux_v3_cfg_t const uart1_pads[] = { | |
71 | MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
72 | MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
73 | }; | |
74 | ||
75 | iomux_v3_cfg_t const uart4_pads[] = { | |
76 | MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
77 | MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
78 | MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
79 | MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
80 | }; | |
81 | ||
82 | iomux_v3_cfg_t const uart5_pads[] = { | |
83 | MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
84 | MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
85 | MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
86 | MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
87 | }; | |
88 | ||
89 | iomux_v3_cfg_t const i2c0_mux_pads[] = { | |
90 | MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
91 | MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
92 | MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
93 | }; | |
94 | ||
95 | iomux_v3_cfg_t const i2c2_mux_pads[] = { | |
96 | MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
97 | MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
98 | MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
99 | }; | |
100 | ||
101 | struct i2c_pads_info i2c_pad_info0 = { | |
102 | .scl = { | |
103 | .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, | |
104 | .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, | |
105 | .gp = IMX_GPIO_NR(5, 27) | |
106 | }, | |
107 | .sda = { | |
108 | .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, | |
109 | .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, | |
110 | .gp = IMX_GPIO_NR(5, 26) | |
111 | } | |
112 | }; | |
113 | ||
114 | struct i2c_pads_info i2c_pad_info2 = { | |
115 | .scl = { | |
116 | .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, | |
117 | .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, | |
118 | .gp = IMX_GPIO_NR(1, 3) | |
119 | }, | |
120 | .sda = { | |
121 | .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, | |
122 | .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, | |
123 | .gp = IMX_GPIO_NR(1, 6) | |
124 | } | |
125 | }; | |
126 | ||
127 | /* | |
128 | * This enet related pin-muxing and GPIO handling is done | |
129 | * in SPL U-Boot. For early initialization. And to give the | |
130 | * PHY some time to come out of reset before the U-Boot | |
131 | * ethernet driver tries to access its registers via MDIO. | |
132 | */ | |
133 | int platinum_setup_enet(void) | |
134 | { | |
135 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
136 | unsigned phy_reset = IMX_GPIO_NR(1, 19); | |
137 | ||
138 | /* First configure PHY reset GPIO pin */ | |
139 | imx_iomux_v3_setup_pad(phy_reset_pad); | |
140 | ||
141 | /* Reconfigure enet muxing while PHY is in reset */ | |
142 | gpio_direction_output(phy_reset, 0); | |
143 | imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); | |
144 | mdelay(10); | |
145 | gpio_set_value(phy_reset, 1); | |
146 | udelay(100); | |
147 | ||
148 | /* set GPIO_16 as ENET_REF_CLK_OUT */ | |
149 | setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); | |
150 | ||
6d97dc10 | 151 | return enable_fec_anatop_clock(0, ENET_50MHZ); |
5d6050fd SR |
152 | } |
153 | ||
154 | int platinum_setup_i2c(void) | |
155 | { | |
156 | imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads, | |
157 | ARRAY_SIZE(i2c0_mux_pads)); | |
158 | imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads, | |
159 | ARRAY_SIZE(i2c2_mux_pads)); | |
160 | ||
161 | mdelay(10); | |
162 | ||
163 | /* Disable i2c mux 0 */ | |
164 | gpio_direction_output(GPIO_I2C0_SEL0, 0); | |
165 | gpio_direction_output(GPIO_I2C0_SEL1, 0); | |
166 | gpio_direction_output(GPIO_I2C0_ENBN, 1); | |
167 | ||
168 | /* Disable i2c mux 1 */ | |
169 | gpio_direction_output(GPIO_I2C2_SEL0, 0); | |
170 | gpio_direction_output(GPIO_I2C2_SEL1, 0); | |
171 | gpio_direction_output(GPIO_I2C2_ENBN, 1); | |
172 | ||
173 | udelay(10); | |
174 | ||
175 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); | |
176 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); | |
177 | ||
178 | /* Disable all leds */ | |
179 | i2c_set_bus_num(0); | |
180 | i2c_reg_write(0x60, 0x05, 0x55); | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | int platinum_setup_spi(void) | |
186 | { | |
187 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); | |
188 | imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); | |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
193 | int platinum_setup_uart(void) | |
194 | { | |
195 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); | |
196 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); | |
197 | imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
202 | int platinum_phy_config(struct phy_device *phydev) | |
203 | { | |
204 | /* Use generic infrastructure, no specific setup */ | |
205 | if (phydev->drv->config) | |
206 | phydev->drv->config(phydev); | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | int platinum_init_gpio(void) | |
212 | { | |
213 | /* Reset FPGA's */ | |
214 | gpio_direction_output(GPIO_IP_NCONFIG, 0); | |
215 | gpio_direction_output(GPIO_HK_NCONFIG, 0); | |
216 | gpio_direction_output(GPIO_LS_NCONFIG, 0); | |
217 | udelay(3); | |
218 | gpio_set_value(GPIO_IP_NCONFIG, 1); | |
219 | gpio_set_value(GPIO_HK_NCONFIG, 1); | |
220 | gpio_set_value(GPIO_LS_NCONFIG, 1); | |
221 | ||
222 | /* no dmd configuration yet */ | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | int platinum_init_usb(void) | |
228 | { | |
229 | /* Reset usb hub */ | |
230 | gpio_direction_output(GPIO_USB_RESET, 0); | |
231 | udelay(100); | |
232 | gpio_set_value(GPIO_USB_RESET, 1); | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
237 | int platinum_init_finished(void) | |
238 | { | |
239 | /* Enable led 0 */ | |
240 | i2c_set_bus_num(0); | |
241 | i2c_reg_write(0x60, 0x05, 0x54); | |
242 | ||
243 | return 0; | |
244 | } |