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1 | /******************************************************************** |
2 | * | |
3 | * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms | |
4 | * | |
5 | * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/speed.h,v $ | |
6 | * $Revision: 1.2 $ | |
7 | * $Author: mleeman $ | |
8 | * $Date: 2005/02/21 12:48:58 $ | |
9 | * | |
10 | * Last ChangeLog Entry | |
11 | * $Log: speed.h,v $ | |
12 | * Revision 1.2 2005/02/21 12:48:58 mleeman | |
13 | * update of copyright years (feedback wd) | |
14 | * | |
15 | * Revision 1.1 2005/02/14 09:23:46 mleeman | |
16 | * - moved 'barcohydra' directory to a more generic barco; since we will be | |
17 | * supporting and adding multiple boards | |
18 | * | |
19 | * Revision 1.2 2005/02/09 12:56:23 mleeman | |
20 | * add generic header to track changes in sources | |
21 | * | |
22 | * | |
23 | *******************************************************************/ | |
24 | ||
25 | /* | |
26 | * (C) Copyright 2000 | |
27 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
28 | * | |
29 | * See file CREDITS for list of people who contributed to this | |
30 | * project. | |
31 | * | |
32 | * This program is free software; you can redistribute it and/or | |
33 | * modify it under the terms of the GNU General Public License as | |
34 | * published by the Free Software Foundation; either version 2 of | |
35 | * the License, or (at your option) any later version. | |
36 | * | |
37 | * This program is distributed in the hope that it will be useful, | |
38 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
39 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
40 | * GNU General Public License for more details. | |
41 | * | |
42 | * You should have received a copy of the GNU General Public License | |
43 | * along with this program; if not, write to the Free Software | |
44 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
45 | * MA 02111-1307 USA | |
46 | */ | |
47 | ||
48 | /*----------------------------------------------------------------------- | |
49 | * Timer value for timer 2, ICLK = 10 | |
50 | * | |
51 | * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) | |
52 | * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 | |
53 | * | |
54 | * SPEED_FCOUNT2 timer 2 counting frequency | |
53677ef1 | 55 | * GCLK CPU clock |
8e6f1a8e WD |
56 | * SPEED_TMR2_PS prescaler |
57 | */ | |
53677ef1 | 58 | #define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ |
8e6f1a8e WD |
59 | |
60 | /*----------------------------------------------------------------------- | |
61 | * Timer value for PIT | |
62 | * | |
63 | * PIT_TIME = SPEED_PITC / PITRTCLK | |
64 | * PITRTCLK = 8192 | |
65 | */ | |
66 | #define SPEED_PITC (82 << 16) /* start counting from 82 */ | |
67 | ||
68 | /* | |
69 | * The new value for PTA is calculated from | |
70 | * | |
71 | * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) | |
72 | * | |
73 | * gclk CPU clock (not bus clock !) | |
74 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
75 | * DFBRG For normal mode (no clock reduction) always 0 | |
76 | * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) | |
77 | * NCS Number of SDRAM banks (chip selects) on this UPM. | |
78 | */ |