[people/ms/u-boot.git] / board / bf527-ezkit / video.c

/*
 * video.c - run splash screen on lcd
 *
 * Copyright (c) 2007-2008 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <stdarg.h>
#include <common.h>
#include <config.h>
#include <malloc.h>
#include <asm/blackfin.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <spi.h>
#include <linux/types.h>
#include <stdio_dev.h>

#include <asm/mach-common/bits/ppi.h>
#include <asm/mach-common/bits/timer.h>

#define LCD_X_RES		320	/* Horizontal Resolution */
#define LCD_Y_RES		240	/* Vertical Resolution */
#define DMA_BUS_SIZE		16

#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */

#if !defined(CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI) && \
    !defined(CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI)
# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
#endif

/* Interface 16/18-bit TFT over an 8-bit wide PPI using a
 * small Programmable Logic Device (CPLD)
 * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
 */

#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
#include <asm/bfin_logo_rgb565_230x230.h>
#define LCD_BPP		16	/* Bit Per Pixel */
#define CLOCKS_PPIX	2	/* Clocks per pixel */
#define CPLD_DELAY	3	/* RGB565 pipeline delay */
#endif

#ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
#include <asm/bfin_logo_230x230.h>
#define LCD_BPP		24	/* Bit Per Pixel */
#define CLOCKS_PPIX	3	/* Clocks per pixel */
#define CPLD_DELAY	5	/* RGB888 pipeline delay */
#endif

/*
 * HS and VS timing parameters (all in number of PPI clk ticks)
 */

#define H_ACTPIX	(LCD_X_RES * CLOCKS_PPIX)	/* active horizontal pixel */
#define H_PERIOD	(336 * CLOCKS_PPIX)		/* HS period */
#define H_PULSE		(2 * CLOCKS_PPIX)		/* HS pulse width */
#define H_START		(7 * CLOCKS_PPIX + CPLD_DELAY)	/* first valid pixel */

#define U_LINE		4				/* Blanking Lines */

#define V_LINES		(LCD_Y_RES + U_LINE)		/* total vertical lines */
#define V_PULSE		(2 * CLOCKS_PPIX)		/* VS pulse width (1-5 H_PERIODs) */
#define V_PERIOD	(H_PERIOD * V_LINES)		/* VS period */

#define ACTIVE_VIDEO_MEM_OFFSET	((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))

/*
 * LCD Modes
 */
#define LQ035_RL	(0 << 8)	/* Right -> Left Scan */
#define LQ035_LR	(1 << 8)	/* Left -> Right Scan */
#define LQ035_TB	(1 << 9)	/* Top -> Botton Scan */
#define LQ035_BT	(0 << 9)	/* Botton -> Top Scan */
#define LQ035_BGR	(1 << 11)	/* Use BGR format */
#define LQ035_RGB	(0 << 11)	/* Use RGB format */
#define LQ035_NORM	(1 << 13)	/* Reversal */
#define LQ035_REV	(0 << 13)	/* Reversal */

#define LQ035_INDEX			0x74
#define LQ035_DATA			0x76

#define LQ035_DRIVER_OUTPUT_CTL		0x1
#define LQ035_SHUT_CTL			0x11

#define LQ035_DRIVER_OUTPUT_MASK	(LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
#define LQ035_DRIVER_OUTPUT_DEFAULT	(0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)

#define LQ035_SHUT			(1 << 0)	/* Shutdown */
#define LQ035_ON			(0 << 0)	/* Shutdown */

#ifndef CONFIG_LQ035Q1_LCD_MODE
#define CONFIG_LQ035Q1_LCD_MODE		(LQ035_NORM | LQ035_RL | LQ035_TB | LQ035_BGR)
#endif

#else /* t350mcqb */
#include <asm/bfin_logo_230x230.h>

#define LCD_BPP		24	/* Bit Per Pixel */
#define CLOCKS_PPIX	3	/* Clocks per pixel */

/* HS and VS timing parameters (all in number of PPI clk ticks) */
#define H_ACTPIX	(LCD_X_RES * CLOCKS_PPIX)	/* active horizontal pixel */
#define H_PERIOD	(408 * CLOCKS_PPIX)		/* HS period */
#define H_PULSE		90				/* HS pulse width */
#define H_START		204				/* first valid pixel */

#define U_LINE		1				/* Blanking Lines */

#define V_LINES		(LCD_Y_RES + U_LINE)		/* total vertical lines */
#define V_PULSE		(3 * H_PERIOD)			/* VS pulse width (1-5 H_PERIODs) */
#define V_PERIOD	(H_PERIOD * V_LINES)		/* VS period */

#define ACTIVE_VIDEO_MEM_OFFSET	(U_LINE * H_ACTPIX)
#endif

#define LCD_PIXEL_SIZE		(LCD_BPP / 8)
#define DMA_SIZE16		2

#define PPI_TX_MODE		0x2
#define PPI_XFER_TYPE_11	0xC
#define PPI_PORT_CFG_01		0x10
#define PPI_PACK_EN		0x80
#define PPI_POLS_1		0x8000

#ifdef CONFIG_BF527_EZKIT_REV_2_1
static struct spi_slave *slave;
static int lq035q1_control(unsigned char reg, unsigned short value)
{
	int ret;
	u8 regs[3] = {LQ035_INDEX, 0, 0};
	u8 data[3] = {LQ035_DATA, 0, 0};
	u8 dummy[3];

	regs[2] = reg;
	data[1] = value >> 8;
	data[2] = value & 0xFF;

	if (!slave) {
		/* FIXME: Verify the max SCK rate */
		slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
				CONFIG_LQ035Q1_SPI_CS, 20000000,
				SPI_MODE_3);
		if (!slave)
			return -1;
	}

	if (spi_claim_bus(slave))
		return -1;

	ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
	ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);

	spi_release_bus(slave);

	return ret;
}
#endif

/* enable and disable PPI functions */
void EnablePPI(void)
{
	bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
}

void DisablePPI(void)
{
	bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
}

void Init_Ports(void)
{
	const unsigned short pins[] = {
		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0,
	};
	peripheral_request_list(pins, "lcd");
}

void Init_PPI(void)
{

	bfin_write_PPI_DELAY(H_START);
	bfin_write_PPI_COUNT(H_ACTPIX - 1);
	bfin_write_PPI_FRAME(V_LINES);

	/* PPI control, to be replaced with definitions */
	bfin_write_PPI_CONTROL(
			PPI_TX_MODE		|	/* output mode , PORT_DIR */
			PPI_XFER_TYPE_11	|	/* sync mode XFR_TYPE */
			PPI_PORT_CFG_01		|	/* two frame sync PORT_CFG */
			PPI_PACK_EN		|	/* packing enabled PACK_EN */
			PPI_POLS_1			/* faling edge syncs POLS */
	);
}

void Init_DMA(void *dst)
{
	bfin_write_DMA0_START_ADDR(dst);

	/* X count */
	bfin_write_DMA0_X_COUNT(H_ACTPIX / 2);
	bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8);

	/* Y count */
	bfin_write_DMA0_Y_COUNT(V_LINES);
	bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8);

	/* DMA Config */
	bfin_write_DMA0_CONFIG(
		WDSIZE_16	|	/* 16 bit DMA */
		DMA2D 		|	/* 2D DMA */
		FLOW_AUTO		/* autobuffer mode */
	);
}

void EnableDMA(void)
{
	bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() | DMAEN);
}

void DisableDMA(void)
{
	bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
}

/* Init TIMER0 as Frame Sync 1 generator */
void InitTIMER0(void)
{
	bfin_write_TIMER_DISABLE(TIMDIS0);			/* disable Timer */
	SSYNC();
	bfin_write_TIMER_STATUS(TIMIL0 | TOVF_ERR0 | TRUN0);	/* clear status */
	SSYNC();

	bfin_write_TIMER0_PERIOD(H_PERIOD);
	SSYNC();
	bfin_write_TIMER0_WIDTH(H_PULSE);
	SSYNC();

	bfin_write_TIMER0_CONFIG(
				PWM_OUT |
				PERIOD_CNT   |
				TIN_SEL      |
				CLK_SEL      |
				EMU_RUN
	);
	SSYNC();
}

void EnableTIMER0(void)
{
	bfin_write_TIMER_ENABLE(TIMEN0);
	SSYNC();
}

void DisableTIMER0(void)
{
	bfin_write_TIMER_DISABLE(TIMDIS0);
	SSYNC();
}


void InitTIMER1(void)
{
	bfin_write_TIMER_DISABLE(TIMDIS1);			/* disable Timer */
	SSYNC();
	bfin_write_TIMER_STATUS(TIMIL1 | TOVF_ERR1 | TRUN1);	/* clear status */
	SSYNC();

	bfin_write_TIMER1_PERIOD(V_PERIOD);
	SSYNC();
	bfin_write_TIMER1_WIDTH(V_PULSE);
	SSYNC();

	bfin_write_TIMER1_CONFIG(
				PWM_OUT |
				PERIOD_CNT   |
				TIN_SEL      |
				CLK_SEL      |
				EMU_RUN
	);
	SSYNC();
}

void EnableTIMER1(void)
{
	bfin_write_TIMER_ENABLE(TIMEN1);
	SSYNC();
}

void DisableTIMER1(void)
{
	bfin_write_TIMER_DISABLE(TIMDIS1);
	SSYNC();
}

void EnableTIMER12(void)
{
	bfin_write_TIMER_ENABLE(TIMEN1 | TIMEN0);
	SSYNC();
}

int video_init(void *dst)
{

#ifdef CONFIG_BF527_EZKIT_REV_2_1
	lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
	lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
		LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT);
#endif
	Init_Ports();
	Init_DMA(dst);
	EnableDMA();
	InitTIMER0();
	InitTIMER1();
	Init_PPI();
	EnablePPI();

#ifdef CONFIG_BF527_EZKIT_REV_2_1
	EnableTIMER12();
#else
	/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
	EnableTIMER1();
	/* Add Some Delay ... */
	SSYNC();
	SSYNC();
	SSYNC();
	SSYNC();

	/* now start frame sync 1 */
	EnableTIMER0();
#endif

	return 0;
}

static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
{
	if (dcache_status())
		blackfin_dcache_flush_range(logo->data, logo->data + logo->size);

	bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);

	/* Setup destination start address */
	bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
					+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
	/* Setup destination xcount */
	bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
	/* Setup destination xmodify */
	bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);

	/* Setup destination ycount */
	bfin_write_MDMA_D0_Y_COUNT(logo->height);
	/* Setup destination ymodify */
	bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);


	/* Setup Source start address */
	bfin_write_MDMA_S0_START_ADDR(logo->data);
	/* Setup Source xcount */
	bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
	/* Setup Source xmodify */
	bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);

	/* Setup Source ycount */
	bfin_write_MDMA_S0_Y_COUNT(logo->height);
	/* Setup Source ymodify */
	bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);


	/* Enable source DMA */
	bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
	SSYNC();
	bfin_write_MDMA_D0_CONFIG(WNR | DMAEN  | WDSIZE_16 | DMA2D);

	while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);

	bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
	bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);

}

void video_stop(void)
{
	DisablePPI();
	DisableDMA();
	DisableTIMER0();
	DisableTIMER1();
#ifdef CONFIG_BF527_EZKIT_REV_2_1
	lq035q1_control(LQ035_SHUT_CTL, LQ035_SHUT);
#endif
}

void video_putc(const char c)
{
}

void video_puts(const char *s)
{
}

int drv_video_init(void)
{
	int error, devices = 1;
	struct stdio_dev videodev;

	u8 *dst;
	u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;

	dst = malloc(fbmem_size);

	if (dst == NULL) {
		printf("Failed to alloc FB memory\n");
		return -1;
	}

#ifdef EASYLOGO_ENABLE_GZIP
	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
	if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
		puts("Failed to decompress logo\n");
		free(dst);
		return -1;
	}
	bfin_logo.data = data;
#endif

	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);

	dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
			(LCD_X_RES - bfin_logo.width) / 2,
			(LCD_Y_RES - bfin_logo.height) / 2);

	video_init(dst);		/* Video initialization */

	memset(&videodev, 0, sizeof(videodev));

	strcpy(videodev.name, "video");
	videodev.ext = DEV_EXT_VIDEO;	/* Video extensions */
	videodev.flags = DEV_FLAGS_SYSTEM;	/* No Output */
	videodev.putc = video_putc;	/* 'putc' function */
	videodev.puts = video_puts;	/* 'puts' function */

	error = stdio_register(&videodev);

	return (error == 0) ? devices : error;
}
Commit	Line	Data
d9a5d113 MF	1	/*
	2	* video.c - run splash screen on lcd
	3	*
	4	* Copyright (c) 2007-2008 Analog Devices Inc.
	5	*
	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	#include <stdarg.h>
	10	#include <common.h>
	11	#include <config.h>
	12	#include <malloc.h>
	13	#include <asm/blackfin.h>
22e64405	14	#include <asm/portmux.h>
d9a5d113	15	#include <asm/mach-common/bits/dma.h>
10eafa10	16	#include <spi.h>
d9a5d113	17	#include <linux/types.h>
52cb4d4f	18	#include <stdio_dev.h>
d9a5d113	19
d9a5d113 MF	20	#include <asm/mach-common/bits/ppi.h>
	21	#include <asm/mach-common/bits/timer.h>
	22
d9a5d113 MF	23	#define LCD_X_RES 320 /* Horizontal Resolution */
d9a5d113 MF	24	#define LCD_Y_RES 240 /* Vertical Resolution */
10eafa10 MH	25	#define DMA_BUS_SIZE 16
10eafa10 MH	26
d24f2d32	27	#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */
10eafa10 MH	28
	29	#if !defined(CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI) && \
	30	!defined(CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI)
	31	# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
	32	#endif
	33
	34	/* Interface 16/18-bit TFT over an 8-bit wide PPI using a
	35	* small Programmable Logic Device (CPLD)
	36	* http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
	37	*/
	38
	39	#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
	40	#include <asm/bfin_logo_rgb565_230x230.h>
	41	#define LCD_BPP 16 /* Bit Per Pixel */
	42	#define CLOCKS_PPIX 2 /* Clocks per pixel */
	43	#define CPLD_DELAY 3 /* RGB565 pipeline delay */
	44	#endif
	45
	46	#ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
	47	#include <asm/bfin_logo_230x230.h>
	48	#define LCD_BPP 24 /* Bit Per Pixel */
	49	#define CLOCKS_PPIX 3 /* Clocks per pixel */
	50	#define CPLD_DELAY 5 /* RGB888 pipeline delay */
	51	#endif
	52
	53	/*
	54	* HS and VS timing parameters (all in number of PPI clk ticks)
	55	*/
	56
	57	#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
	58	#define H_PERIOD (336 * CLOCKS_PPIX) /* HS period */
	59	#define H_PULSE (2 * CLOCKS_PPIX) /* HS pulse width */
	60	#define H_START (7 * CLOCKS_PPIX + CPLD_DELAY) /* first valid pixel */
	61
	62	#define U_LINE 4 /* Blanking Lines */
	63
	64	#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
	65	#define V_PULSE (2 * CLOCKS_PPIX) /* VS pulse width (1-5 H_PERIODs) */
	66	#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
	67
	68	#define ACTIVE_VIDEO_MEM_OFFSET ((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
	69
	70	/*
	71	* LCD Modes
	72	*/
	73	#define LQ035_RL (0 << 8) /* Right -> Left Scan */
	74	#define LQ035_LR (1 << 8) /* Left -> Right Scan */
	75	#define LQ035_TB (1 << 9) /* Top -> Botton Scan */
	76	#define LQ035_BT (0 << 9) /* Botton -> Top Scan */
	77	#define LQ035_BGR (1 << 11) /* Use BGR format */
	78	#define LQ035_RGB (0 << 11) /* Use RGB format */
	79	#define LQ035_NORM (1 << 13) /* Reversal */
	80	#define LQ035_REV (0 << 13) /* Reversal */
d9a5d113	81
10eafa10 MH	82	#define LQ035_INDEX 0x74
10eafa10 MH	83	#define LQ035_DATA 0x76
d9a5d113	84
10eafa10 MH	85	#define LQ035_DRIVER_OUTPUT_CTL 0x1
	86	#define LQ035_SHUT_CTL 0x11
	87
	88	#define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR \| LQ035_TB \| LQ035_BGR \| LQ035_REV)
	89	#define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
	90
	91	#define LQ035_SHUT (1 << 0) /* Shutdown */
	92	#define LQ035_ON (0 << 0) /* Shutdown */
	93
	94	#ifndef CONFIG_LQ035Q1_LCD_MODE
	95	#define CONFIG_LQ035Q1_LCD_MODE (LQ035_NORM \| LQ035_RL \| LQ035_TB \| LQ035_BGR)
	96	#endif
	97
	98	#else /* t350mcqb */
	99	#include <asm/bfin_logo_230x230.h>
	100
	101	#define LCD_BPP 24 /* Bit Per Pixel */
	102	#define CLOCKS_PPIX 3 /* Clocks per pixel */
d9a5d113 MF	103
d9a5d113 MF	104	/* HS and VS timing parameters (all in number of PPI clk ticks) */
10eafa10 MH	105	#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
10eafa10 MH	106	#define H_PERIOD (408 * CLOCKS_PPIX) /* HS period */
d9a5d113 MF	107	#define H_PULSE 90 /* HS pulse width */
	108	#define H_START 204 /* first valid pixel */
	109
	110	#define U_LINE 1 /* Blanking Lines */
	111
10eafa10	112	#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
d9a5d113 MF	113	#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
	114	#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
	115
	116	#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
10eafa10 MH	117	#endif
	118
	119	#define LCD_PIXEL_SIZE (LCD_BPP / 8)
	120	#define DMA_SIZE16 2
d9a5d113 MF	121
	122	#define PPI_TX_MODE 0x2
	123	#define PPI_XFER_TYPE_11 0xC
	124	#define PPI_PORT_CFG_01 0x10
	125	#define PPI_PACK_EN 0x80
	126	#define PPI_POLS_1 0x8000
	127
d24f2d32	128	#ifdef CONFIG_BF527_EZKIT_REV_2_1
10eafa10 MH	129	static struct spi_slave *slave;
	130	static int lq035q1_control(unsigned char reg, unsigned short value)
	131	{
	132	int ret;
	133	u8 regs[3] = {LQ035_INDEX, 0, 0};
	134	u8 data[3] = {LQ035_DATA, 0, 0};
	135	u8 dummy[3];
	136
	137	regs[2] = reg;
	138	data[1] = value >> 8;
	139	data[2] = value & 0xFF;
	140
	141	if (!slave) {
	142	/* FIXME: Verify the max SCK rate */
	143	slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
	144	CONFIG_LQ035Q1_SPI_CS, 20000000,
	145	SPI_MODE_3);
	146	if (!slave)
	147	return -1;
	148	}
	149
	150	if (spi_claim_bus(slave))
	151	return -1;
	152
	153	ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN \| SPI_XFER_END);
	154	ret \|= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN \| SPI_XFER_END);
	155
	156	spi_release_bus(slave);
	157
	158	return ret;
	159	}
	160	#endif
	161
d9a5d113 MF	162	/* enable and disable PPI functions */
	163	void EnablePPI(void)
	164	{
989ab87e	165	bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() \| PORT_EN);
d9a5d113 MF	166	}
	167
	168	void DisablePPI(void)
	169	{
989ab87e	170	bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
d9a5d113 MF	171	}
	172
	173	void Init_Ports(void)
	174	{
22e64405 MF	175	const unsigned short pins[] = {
	176	P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
	177	P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0,
	178	};
	179	peripheral_request_list(pins, "lcd");
d9a5d113 MF	180	}
	181
	182	void Init_PPI(void)
	183	{
	184
989ab87e MF	185	bfin_write_PPI_DELAY(H_START);
	186	bfin_write_PPI_COUNT(H_ACTPIX - 1);
	187	bfin_write_PPI_FRAME(V_LINES);
d9a5d113 MF	188
d9a5d113 MF	189	/* PPI control, to be replaced with definitions */
989ab87e MF	190	bfin_write_PPI_CONTROL(
989ab87e MF	191	PPI_TX_MODE \| /* output mode , PORT_DIR */
d9a5d113 MF	192	PPI_XFER_TYPE_11 \| /* sync mode XFR_TYPE */
	193	PPI_PORT_CFG_01 \| /* two frame sync PORT_CFG */
	194	PPI_PACK_EN \| /* packing enabled PACK_EN */
989ab87e MF	195	PPI_POLS_1 /* faling edge syncs POLS */
989ab87e MF	196	);
d9a5d113 MF	197	}
	198
	199	void Init_DMA(void *dst)
	200	{
989ab87e	201	bfin_write_DMA0_START_ADDR(dst);
d9a5d113 MF	202
d9a5d113 MF	203	/* X count */
989ab87e MF	204	bfin_write_DMA0_X_COUNT(H_ACTPIX / 2);
989ab87e MF	205	bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8);
d9a5d113 MF	206
d9a5d113 MF	207	/* Y count */
989ab87e MF	208	bfin_write_DMA0_Y_COUNT(V_LINES);
989ab87e MF	209	bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8);
d9a5d113 MF	210
d9a5d113 MF	211	/* DMA Config */
989ab87e	212	bfin_write_DMA0_CONFIG(
d9a5d113 MF	213	WDSIZE_16 \| /* 16 bit DMA */
d9a5d113 MF	214	DMA2D \| /* 2D DMA */
989ab87e MF	215	FLOW_AUTO /* autobuffer mode */
989ab87e MF	216	);
d9a5d113 MF	217	}
d9a5d113 MF	218
d9a5d113 MF	219	void EnableDMA(void)
d9a5d113 MF	220	{
989ab87e	221	bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() \| DMAEN);
d9a5d113 MF	222	}
	223
	224	void DisableDMA(void)
	225	{
989ab87e	226	bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
d9a5d113 MF	227	}
d9a5d113 MF	228
d9a5d113 MF	229	/* Init TIMER0 as Frame Sync 1 generator */
	230	void InitTIMER0(void)
	231	{
989ab87e	232	bfin_write_TIMER_DISABLE(TIMDIS0); /* disable Timer */
d9a5d113	233	SSYNC();
989ab87e	234	bfin_write_TIMER_STATUS(TIMIL0 \| TOVF_ERR0 \| TRUN0); /* clear status */
d9a5d113 MF	235	SSYNC();
d9a5d113 MF	236
989ab87e	237	bfin_write_TIMER0_PERIOD(H_PERIOD);
d9a5d113	238	SSYNC();
989ab87e	239	bfin_write_TIMER0_WIDTH(H_PULSE);
d9a5d113 MF	240	SSYNC();
d9a5d113 MF	241
989ab87e MF	242	bfin_write_TIMER0_CONFIG(
989ab87e MF	243	PWM_OUT \|
d9a5d113 MF	244	PERIOD_CNT \|
	245	TIN_SEL \|
	246	CLK_SEL \|
989ab87e MF	247	EMU_RUN
989ab87e MF	248	);
d9a5d113 MF	249	SSYNC();
	250	}
	251
	252	void EnableTIMER0(void)
	253	{
989ab87e	254	bfin_write_TIMER_ENABLE(TIMEN0);
d9a5d113 MF	255	SSYNC();
	256	}
	257
	258	void DisableTIMER0(void)
	259	{
989ab87e	260	bfin_write_TIMER_DISABLE(TIMDIS0);
d9a5d113 MF	261	SSYNC();
	262	}
	263
	264
	265	void InitTIMER1(void)
	266	{
989ab87e	267	bfin_write_TIMER_DISABLE(TIMDIS1); /* disable Timer */
d9a5d113	268	SSYNC();
989ab87e	269	bfin_write_TIMER_STATUS(TIMIL1 \| TOVF_ERR1 \| TRUN1); /* clear status */
d9a5d113 MF	270	SSYNC();
d9a5d113 MF	271
989ab87e	272	bfin_write_TIMER1_PERIOD(V_PERIOD);
d9a5d113	273	SSYNC();
989ab87e	274	bfin_write_TIMER1_WIDTH(V_PULSE);
d9a5d113 MF	275	SSYNC();
d9a5d113 MF	276
989ab87e MF	277	bfin_write_TIMER1_CONFIG(
989ab87e MF	278	PWM_OUT \|
d9a5d113 MF	279	PERIOD_CNT \|
	280	TIN_SEL \|
	281	CLK_SEL \|
989ab87e MF	282	EMU_RUN
989ab87e MF	283	);
d9a5d113 MF	284	SSYNC();
	285	}
	286
	287	void EnableTIMER1(void)
	288	{
989ab87e	289	bfin_write_TIMER_ENABLE(TIMEN1);
d9a5d113 MF	290	SSYNC();
	291	}
	292
	293	void DisableTIMER1(void)
	294	{
989ab87e	295	bfin_write_TIMER_DISABLE(TIMDIS1);
d9a5d113 MF	296	SSYNC();
	297	}
	298
10eafa10 MH	299	void EnableTIMER12(void)
10eafa10 MH	300	{
989ab87e	301	bfin_write_TIMER_ENABLE(TIMEN1 \| TIMEN0);
10eafa10 MH	302	SSYNC();
	303	}
	304
d9a5d113 MF	305	int video_init(void *dst)
	306	{
	307
d24f2d32	308	#ifdef CONFIG_BF527_EZKIT_REV_2_1
10eafa10 MH	309	lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
	310	lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
	311	LQ035_DRIVER_OUTPUT_MASK) \| LQ035_DRIVER_OUTPUT_DEFAULT);
	312	#endif
d9a5d113 MF	313	Init_Ports();
	314	Init_DMA(dst);
	315	EnableDMA();
	316	InitTIMER0();
	317	InitTIMER1();
	318	Init_PPI();
	319	EnablePPI();
	320
d24f2d32	321	#ifdef CONFIG_BF527_EZKIT_REV_2_1
10eafa10 MH	322	EnableTIMER12();
10eafa10 MH	323	#else
d9a5d113 MF	324	/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
	325	EnableTIMER1();
	326	/* Add Some Delay ... */
	327	SSYNC();
	328	SSYNC();
	329	SSYNC();
	330	SSYNC();
	331
	332	/* now start frame sync 1 */
	333	EnableTIMER0();
10eafa10	334	#endif
d9a5d113 MF	335
	336	return 0;
	337	}
	338
	339	static void dma_bitblit(void dst, fastimage_t logo, int x, int y)
	340	{
	341	if (dcache_status())
	342	blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
	343
	344	bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE \| DMA_ERR);
	345
	346	/* Setup destination start address */
	347	bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
	348	+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
	349	/* Setup destination xcount */
	350	bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
	351	/* Setup destination xmodify */
	352	bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
	353
	354	/* Setup destination ycount */
	355	bfin_write_MDMA_D0_Y_COUNT(logo->height);
	356	/* Setup destination ymodify */
	357	bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
	358
	359
	360	/* Setup Source start address */
	361	bfin_write_MDMA_S0_START_ADDR(logo->data);
	362	/* Setup Source xcount */
	363	bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
	364	/* Setup Source xmodify */
	365	bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
	366
	367	/* Setup Source ycount */
	368	bfin_write_MDMA_S0_Y_COUNT(logo->height);
	369	/* Setup Source ymodify */
	370	bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
	371
	372
	373	/* Enable source DMA */
	374	bfin_write_MDMA_S0_CONFIG(DMAEN \| WDSIZE_16 \| DMA2D);
	375	SSYNC();
	376	bfin_write_MDMA_D0_CONFIG(WNR \| DMAEN \| WDSIZE_16 \| DMA2D);
	377
	378	while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
	379
	380	bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() \| DMA_DONE \| DMA_ERR);
	381	bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() \| DMA_DONE \| DMA_ERR);
	382
	383	}
	384
5fc564ed MH	385	void video_stop(void)
	386	{
	387	DisablePPI();
	388	DisableDMA();
	389	DisableTIMER0();
	390	DisableTIMER1();
d24f2d32	391	#ifdef CONFIG_BF527_EZKIT_REV_2_1
5fc564ed MH	392	lq035q1_control(LQ035_SHUT_CTL, LQ035_SHUT);
	393	#endif
	394	}
	395
d9a5d113 MF	396	void video_putc(const char c)
	397	{
	398	}
	399
	400	void video_puts(const char *s)
	401	{
	402	}
	403
	404	int drv_video_init(void)
	405	{
	406	int error, devices = 1;
52cb4d4f	407	struct stdio_dev videodev;
d9a5d113 MF	408
	409	u8 *dst;
	410	u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
	411
	412	dst = malloc(fbmem_size);
	413
	414	if (dst == NULL) {
	415	printf("Failed to alloc FB memory\n");
	416	return -1;
	417	}
	418
	419	#ifdef EASYLOGO_ENABLE_GZIP
	420	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
	421	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
	422	if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
	423	puts("Failed to decompress logo\n");
	424	free(dst);
	425	return -1;
	426	}
	427	bfin_logo.data = data;
	428	#endif
	429
	430	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
	431
	432	dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
	433	(LCD_X_RES - bfin_logo.width) / 2,
	434	(LCD_Y_RES - bfin_logo.height) / 2);
	435
	436	video_init(dst); /* Video initialization */
	437
	438	memset(&videodev, 0, sizeof(videodev));
	439
	440	strcpy(videodev.name, "video");
	441	videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
	442	videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
	443	videodev.putc = video_putc; /* 'putc' function */
	444	videodev.puts = video_puts; /* 'puts' function */
	445
52cb4d4f	446	error = stdio_register(&videodev);
d9a5d113 MF	447
	448	return (error == 0) ? devices : error;
	449	}