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6cb142fa | 1 | /* |
a187559e | 2 | * U-Boot - psd4256.h |
6cb142fa | 3 | * |
155fd766 | 4 | * Copyright (c) 2005-2007 Analog Devices Inc. |
6cb142fa WD |
5 | * |
6 | * (C) Copyright 2000-2004 | |
7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
6cb142fa WD |
10 | */ |
11 | ||
12 | /* | |
13 | * Flash A/B Port A configuration registers. | |
6d0f6bcf JCPV |
14 | * Addresses are offset values to CONFIG_SYS_FLASH1_BASE |
15 | * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B. | |
6cb142fa WD |
16 | */ |
17 | ||
18 | #define PSD_PORTA_DIN 0x070000 | |
19 | #define PSD_PORTA_DOUT 0x070004 | |
20 | #define PSD_PORTA_DIR 0x070006 | |
21 | ||
22 | /* | |
23 | * Flash A/B Port B configuration registers | |
6d0f6bcf JCPV |
24 | * Addresses are offset values to CONFIG_SYS_FLASH1_BASE |
25 | * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B. | |
6cb142fa WD |
26 | */ |
27 | ||
28 | #define PSD_PORTB_DIN 0x070001 | |
29 | #define PSD_PORTB_DOUT 0x070005 | |
30 | #define PSD_PORTB_DIR 0x070007 | |
31 | ||
32 | /* | |
33 | * Flash A Port A Bit definitions | |
34 | */ | |
35 | ||
3f0606ad AL |
36 | #define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */ |
37 | #define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */ | |
38 | #define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */ | |
39 | #define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */ | |
40 | #define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */ | |
6cb142fa WD |
41 | |
42 | /* | |
43 | * Flash A Port B Bit definitions | |
44 | */ | |
45 | ||
3f0606ad AL |
46 | #define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */ |
47 | #define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */ | |
48 | #define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */ | |
49 | #define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */ | |
50 | #define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */ | |
51 | #define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */ |