[thirdparty/u-boot.git] / board / bluewater / snapper9260 / snapper9260.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Bluewater Systems Snapper 9260/9G20 modules
 *
 * (C) Copyright 2011 Bluewater Systems
 *   Author: Andre Renaud <andre@bluewatersys.com>
 *   Author: Ryan Mallon <ryan@bluewatersys.com>
 */

#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/atmel_serial.h>
#include <net.h>
#include <netdev.h>
#include <i2c.h>
#include <pca953x.h>

DECLARE_GLOBAL_DATA_PTR;

/* IO Expander pins */
#define IO_EXP_ETH_RESET	(0 << 1)
#define IO_EXP_ETH_POWER	(1 << 1)

static void macb_hw_init(void)
{
	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;

	at91_periph_clk_enable(ATMEL_ID_EMAC0);

	/* Disable pull-ups to prevent PHY going into test mode */
	writel(pin_to_mask(AT91_PIN_PA14) |
	       pin_to_mask(AT91_PIN_PA15) |
	       pin_to_mask(AT91_PIN_PA18),
	       &pioa->pudr);

	/* Power down ethernet */
	pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);

	/* Hold ethernet in reset */
	pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);

	/* Enable ethernet power */
	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);

	at91_phy_reset();

	/* Bring the ethernet out of reset */
	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);

	/* The phy internal reset take 21ms */
	udelay(21 * 1000);

	/* Re-enable pull-up */
	writel(pin_to_mask(AT91_PIN_PA14) |
	       pin_to_mask(AT91_PIN_PA15) |
	       pin_to_mask(AT91_PIN_PA18),
	       &pioa->puer);

	at91_macb_hw_init();
}

static void nand_hw_init(void)
{
	struct at91_smc *smc       = (struct at91_smc    *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	unsigned long csa;

	/* Enable CS3 as NAND/SmartMedia */
	csa = readl(&matrix->ebicsa);
	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	writel(csa, &matrix->ebicsa);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
	       &smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
	       &smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
	       &smc->cs[3].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
	       AT91_SMC_MODE_EXNW_DISABLE |
	       AT91_SMC_MODE_DBW_8 |
	       AT91_SMC_MODE_TDF_CYCLE(3),
	       &smc->cs[3].mode);

	/* Configure RDY/BSY */
	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);

	/* Enable NandFlash */
	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}

int board_init(void)
{
	at91_periph_clk_enable(ATMEL_ID_PIOA);
	at91_periph_clk_enable(ATMEL_ID_PIOB);
	at91_periph_clk_enable(ATMEL_ID_PIOC);

	/* The mach-type is the same for both Snapper 9260 and 9G20 */
	gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;

	/* Address of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	/* Initialise peripherals */
	at91_seriald_hw_init();
	i2c_set_bus_num(0);
	nand_hw_init();
	macb_hw_init();

	return 0;
}

int board_eth_init(bd_t *bis)
{
	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);
	return 0;
}

void reset_phy(void)
{
}

static struct atmel_serial_platdata at91sam9260_serial_plat = {
	.base_addr = ATMEL_BASE_DBGU,
};

U_BOOT_DEVICE(at91sam9260_serial) = {
	.name	= "serial_atmel",
	.platdata = &at91sam9260_serial_plat,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
b8d41dda RM	2	/*
	3	* Bluewater Systems Snapper 9260/9G20 modules
	4	*
	5	* (C) Copyright 2011 Bluewater Systems
	6	* Author: Andre Renaud <andre@bluewatersys.com>
	7	* Author: Ryan Mallon <ryan@bluewatersys.com>
b8d41dda RM	8	*/
	9
	10	#include <common.h>
1a1927f3	11	#include <dm.h>
b8d41dda	12	#include <asm/io.h>
1a1927f3	13	#include <asm/gpio.h>
c62db35d	14	#include <asm/mach-types.h>
b8d41dda RM	15	#include <asm/arch/at91sam9260_matrix.h>
	16	#include <asm/arch/at91sam9_smc.h>
	17	#include <asm/arch/at91_common.h>
70341e2e	18	#include <asm/arch/clk.h>
b8d41dda	19	#include <asm/arch/gpio.h>
1a1927f3	20	#include <asm/arch/atmel_serial.h>
b8d41dda RM	21	#include <net.h>
	22	#include <netdev.h>
	23	#include <i2c.h>
	24	#include <pca953x.h>
	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
	28	/* IO Expander pins */
	29	#define IO_EXP_ETH_RESET (0 << 1)
	30	#define IO_EXP_ETH_POWER (1 << 1)
	31
	32	static void macb_hw_init(void)
	33	{
b8d41dda	34	struct at91_port pioa = (struct at91_port )ATMEL_BASE_PIOA;
b8d41dda	35
70341e2e	36	at91_periph_clk_enable(ATMEL_ID_EMAC0);
b8d41dda RM	37
	38	/* Disable pull-ups to prevent PHY going into test mode */
	39	writel(pin_to_mask(AT91_PIN_PA14) \|
	40	pin_to_mask(AT91_PIN_PA15) \|
	41	pin_to_mask(AT91_PIN_PA18),
	42	&pioa->pudr);
	43
	44	/* Power down ethernet */
	45	pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
	46	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
	47
	48	/* Hold ethernet in reset */
	49	pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
	50	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
	51
	52	/* Enable ethernet power */
	53	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
	54
4535a24c	55	at91_phy_reset();
b8d41dda RM	56
	57	/* Bring the ethernet out of reset */
	58	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
	59
	60	/* The phy internal reset take 21ms */
	61	udelay(21 * 1000);
	62
	63	/* Re-enable pull-up */
	64	writel(pin_to_mask(AT91_PIN_PA14) \|
	65	pin_to_mask(AT91_PIN_PA15) \|
	66	pin_to_mask(AT91_PIN_PA18),
	67	&pioa->puer);
	68
	69	at91_macb_hw_init();
	70	}
	71
	72	static void nand_hw_init(void)
	73	{
	74	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	75	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
	76	unsigned long csa;
	77
	78	/* Enable CS3 as NAND/SmartMedia */
	79	csa = readl(&matrix->ebicsa);
	80	csa \|= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	81	writel(csa, &matrix->ebicsa);
	82
	83	/* Configure SMC CS3 for NAND/SmartMedia */
	84	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(0) \|
	85	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(0),
	86	&smc->cs[3].setup);
	87	writel(AT91_SMC_PULSE_NWE(4) \| AT91_SMC_PULSE_NCS_WR(4) \|
	88	AT91_SMC_PULSE_NRD(4) \| AT91_SMC_PULSE_NCS_RD(4),
	89	&smc->cs[3].pulse);
	90	writel(AT91_SMC_CYCLE_NWE(7) \| AT91_SMC_CYCLE_NRD(7),
	91	&smc->cs[3].cycle);
	92	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	93	AT91_SMC_MODE_EXNW_DISABLE \|
	94	AT91_SMC_MODE_DBW_8 \|
	95	AT91_SMC_MODE_TDF_CYCLE(3),
	96	&smc->cs[3].mode);
	97
	98	/* Configure RDY/BSY */
1a1927f3 SG	99	gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
1a1927f3 SG	100	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
b8d41dda RM	101
b8d41dda RM	102	/* Enable NandFlash */
1a1927f3 SG	103	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
1a1927f3 SG	104	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
b8d41dda RM	105	}
	106
	107	int board_init(void)
	108	{
70341e2e WY	109	at91_periph_clk_enable(ATMEL_ID_PIOA);
	110	at91_periph_clk_enable(ATMEL_ID_PIOB);
	111	at91_periph_clk_enable(ATMEL_ID_PIOC);
b8d41dda RM	112
	113	/* The mach-type is the same for both Snapper 9260 and 9G20 */
	114	gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
	115
	116	/* Address of boot parameters */
	117	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	118
	119	/* Initialise peripherals */
	120	at91_seriald_hw_init();
ea818dbb	121	i2c_set_bus_num(0);
b8d41dda RM	122	nand_hw_init();
	123	macb_hw_init();
	124
	125	return 0;
	126	}
	127
	128	int board_eth_init(bd_t *bis)
	129	{
	130	return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
	131	}
	132
	133	int dram_init(void)
	134	{
	135	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
	136	CONFIG_SYS_SDRAM_SIZE);
	137	return 0;
	138	}
	139
	140	void reset_phy(void)
	141	{
	142	}
1a1927f3 SG	143
	144	static struct atmel_serial_platdata at91sam9260_serial_plat = {
	145	.base_addr = ATMEL_BASE_DBGU,
	146	};
	147
	148	U_BOOT_DEVICE(at91sam9260_serial) = {
	149	.name = "serial_atmel",
	150	.platdata = &at91sam9260_serial_plat,
	151	};