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nitrogen6x: simplify board_mmc_getcd
[people/ms/u-boot.git] / board / boundary / nitrogen6x / nitrogen6x.c
CommitLineData
d67b0d97
EN		 1/*
2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
4 *
3765b3e7 5 * SPDX-License-Identifier: GPL-2.0+
d67b0d97
EN		 6 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/imx-regs.h>
12#include <asm/arch/iomux.h>
13#include <asm/arch/sys_proto.h>
14#include <malloc.h>
15#include <asm/arch/mx6-pins.h>
16#include <asm/errno.h>
17#include <asm/gpio.h>
18#include <asm/imx-common/iomux-v3.h>
19#include <asm/imx-common/mxc_i2c.h>
164d9846 20#include <asm/imx-common/sata.h>
d67b0d97 21#include <asm/imx-common/boot_mode.h>
a47e4495 22#include <asm/imx-common/video.h>
d67b0d97
EN		 23#include <mmc.h>
24#include <fsl_esdhc.h>
25#include <micrel.h>
26#include <miiphy.h>
27#include <netdev.h>
d67b0d97
EN		 28#include <asm/arch/crm_regs.h>
29#include <asm/arch/mxc_hdmi.h>
30#include <i2c.h>
31
32DECLARE_GLOBAL_DATA_PTR;
08ce074e 33#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
d67b0d97 34
7e2173cf
BT		 35#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
d67b0d97 38
7e2173cf
BT		 39#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
d67b0d97 42
7e2173cf
BT		 43#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
d67b0d97 45
7e2173cf 46#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
d67b0d97
EN		 47 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
48
7e2173cf
BT		 49#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
d67b0d97 51
7e2173cf
BT		 52#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
d67b0d97
EN		 54 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
55
7e2173cf
BT		 56#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
d67b0d97
EN		 58 PAD_CTL_SRE_SLOW)
59
7e2173cf
BT		 60#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
62 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
d67b0d97
EN		 63
64#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
65
66int dram_init(void)
67{
19a0f7fa 68 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
d67b0d97
EN		 69
70 return 0;
71}
72
73iomux_v3_cfg_t const uart1_pads[] = {
10fda487
EN		 74 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
75 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
d67b0d97
EN		 76};
77
78iomux_v3_cfg_t const uart2_pads[] = {
10fda487
EN		 79 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
80 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
d67b0d97
EN		 81};
82
83#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
84
85/* I2C1, SGTL5000 */
86struct i2c_pads_info i2c_pad_info0 = {
87 .scl = {
88 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
10fda487 89 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
d67b0d97
EN		 90 .gp = IMX_GPIO_NR(3, 21)
91 },
92 .sda = {
93 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
10fda487 94 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
d67b0d97
EN		 95 .gp = IMX_GPIO_NR(3, 28)
96 }
97};
98
99/* I2C2 Camera, MIPI */
100struct i2c_pads_info i2c_pad_info1 = {
101 .scl = {
102 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
10fda487 103 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
d67b0d97
EN		 104 .gp = IMX_GPIO_NR(4, 12)
105 },
106 .sda = {
107 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
10fda487 108 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
d67b0d97
EN		 109 .gp = IMX_GPIO_NR(4, 13)
110 }
111};
112
113/* I2C3, J15 - RGB connector */
114struct i2c_pads_info i2c_pad_info2 = {
115 .scl = {
116 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
10fda487 117 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
d67b0d97
EN		 118 .gp = IMX_GPIO_NR(1, 5)
119 },
120 .sda = {
121 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
10fda487 122 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
d67b0d97
EN		 123 .gp = IMX_GPIO_NR(7, 11)
124 }
125};
126
127iomux_v3_cfg_t const usdhc3_pads[] = {
10fda487
EN		 128 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
d67b0d97
EN		 135};
136
137iomux_v3_cfg_t const usdhc4_pads[] = {
10fda487
EN		 138 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
d67b0d97
EN		 145};
146
147iomux_v3_cfg_t const enet_pads1[] = {
148 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
149 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
10fda487
EN		 150 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
151 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
152 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
153 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
154 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
d67b0d97
EN		 155 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
156 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
157 /* pin 35 - 1 (PHY_AD2) on reset */
10fda487 158 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 159 /* pin 32 - 1 - (MODE0) all */
10fda487 160 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 161 /* pin 31 - 1 - (MODE1) all */
10fda487 162 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 163 /* pin 28 - 1 - (MODE2) all */
10fda487 164 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 165 /* pin 27 - 1 - (MODE3) all */
10fda487 166 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 167 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
10fda487 168 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97 169 /* pin 42 PHY nRST */
10fda487
EN		 170 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
171 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97
EN		 172};
173
174iomux_v3_cfg_t const enet_pads2[] = {
10fda487
EN		 175 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
176 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
177 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
178 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
179 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
d67b0d97
EN		 180 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
181};
182
08ce074e
TK		 183static iomux_v3_cfg_t const misc_pads[] = {
184 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
10fda487
EN		 185 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
186 MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
08ce074e 187 /* OTG Power enable */
10fda487 188 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
08ce074e
TK		 189};
190
d67b0d97
EN		 191/* wl1271 pads on nitrogen6x */
192iomux_v3_cfg_t const wl12xx_pads[] = {
10fda487 193 (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
d67b0d97 194 | MUX_PAD_CTRL(WEAK_PULLDOWN),
10fda487 195 (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
d67b0d97 196 | MUX_PAD_CTRL(OUTPUT_40OHM),
10fda487 197 (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
d67b0d97
EN		 198 | MUX_PAD_CTRL(OUTPUT_40OHM),
199};
200#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
201#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
202#define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
203
204/* Button assignments for J14 */
205static iomux_v3_cfg_t const button_pads[] = {
206 /* Menu */
10fda487 207 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97 208 /* Back */
10fda487 209 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97 210 /* Labelled Search (mapped to Power under Android) */
10fda487 211 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97 212 /* Home */
10fda487 213 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97 214 /* Volume Down */
10fda487 215 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97 216 /* Volume Up */
10fda487 217 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
d67b0d97
EN		 218};
219
220static void setup_iomux_enet(void)
221{
222 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
223 gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
224 gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
225 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
226 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
227 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
228 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
229 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
230 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
231
232 /* Need delay 10ms according to KSZ9021 spec */
233 udelay(1000 * 10);
234 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
235 gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
236
237 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
238}
239
240iomux_v3_cfg_t const usb_pads[] = {
10fda487 241 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97
EN		 242};
243
244static void setup_iomux_uart(void)
245{
246 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
247 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
248}
249
250#ifdef CONFIG_USB_EHCI_MX6
251int board_ehci_hcd_init(int port)
252{
253 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
254
255 /* Reset USB hub */
256 gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
257 mdelay(2);
258 gpio_set_value(IMX_GPIO_NR(7, 12), 1);
259
260 return 0;
261}
08ce074e
TK		 262
263int board_ehci_power(int port, int on)
264{
265 if (port)
266 return 0;
267 gpio_set_value(GP_USB_OTG_PWR, on);
268 return 0;
269}
270
d67b0d97
EN		 271#endif
272
273#ifdef CONFIG_FSL_ESDHC
274struct fsl_esdhc_cfg usdhc_cfg[2] = {
275 {USDHC3_BASE_ADDR},
276 {USDHC4_BASE_ADDR},
277};
278
279int board_mmc_getcd(struct mmc *mmc)
280{
281 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
213e9e33
TK		 282 int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
283 IMX_GPIO_NR(2, 6);
d67b0d97 284
213e9e33
TK		 285 gpio_direction_input(gp_cd);
286 return !gpio_get_value(gp_cd);
d67b0d97
EN		 287}
288
289int board_mmc_init(bd_t *bis)
290{
291 s32 status = 0;
292 u32 index = 0;
293
294 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
295 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
296
aad4659a
AR		 297 usdhc_cfg[0].max_bus_width = 4;
298 usdhc_cfg[1].max_bus_width = 4;
299
d67b0d97
EN		 300 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
301 switch (index) {
302 case 0:
303 imx_iomux_v3_setup_multiple_pads(
304 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
305 break;
306 case 1:
307 imx_iomux_v3_setup_multiple_pads(
308 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
309 break;
310 default:
311 printf("Warning: you configured more USDHC controllers"
312 "(%d) then supported by the board (%d)\n",
313 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
314 return status;
315 }
316
317 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
318 }
319
320 return status;
321}
322#endif
323
d67b0d97
EN		 324#ifdef CONFIG_MXC_SPI
325iomux_v3_cfg_t const ecspi1_pads[] = {
326 /* SS1 */
3b31605a 327 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97
EN		 328 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
329 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
330 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
331};
332
333void setup_spi(void)
334{
d67b0d97
EN		 335 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
336 ARRAY_SIZE(ecspi1_pads));
337}
338#endif
339
340int board_phy_config(struct phy_device *phydev)
341{
342 /* min rx data delay */
343 ksz9021_phy_extended_write(phydev,
344 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
345 /* min tx data delay */
346 ksz9021_phy_extended_write(phydev,
347 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
348 /* max rx/tx clock delay, min rx/tx control */
349 ksz9021_phy_extended_write(phydev,
350 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
351 if (phydev->drv->config)
352 phydev->drv->config(phydev);
353
354 return 0;
355}
356
357int board_eth_init(bd_t *bis)
358{
359 uint32_t base = IMX_FEC_BASE;
360 struct mii_dev *bus = NULL;
361 struct phy_device *phydev = NULL;
362 int ret;
363
364 setup_iomux_enet();
365
366#ifdef CONFIG_FEC_MXC
367 bus = fec_get_miibus(base, -1);
368 if (!bus)
369 return 0;
370 /* scan phy 4,5,6,7 */
371 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
372 if (!phydev) {
373 free(bus);
374 return 0;
375 }
376 printf("using phy at %d\n", phydev->addr);
377 ret = fec_probe(bis, -1, base, bus, phydev);
378 if (ret) {
379 printf("FEC MXC: %s:failed\n", __func__);
380 free(phydev);
381 free(bus);
382 }
383#endif
08ce074e 384
f016f8ca 385#ifdef CONFIG_CI_UDC
08ce074e
TK		 386 /* For otg ethernet*/
387 usb_eth_initialize(bis);
388#endif
d67b0d97
EN		 389 return 0;
390}
391
392static void setup_buttons(void)
393{
394 imx_iomux_v3_setup_multiple_pads(button_pads,
395 ARRAY_SIZE(button_pads));
396}
397
d67b0d97
EN		 398#if defined(CONFIG_VIDEO_IPUV3)
399
400static iomux_v3_cfg_t const backlight_pads[] = {
401 /* Backlight on RGB connector: J15 */
10fda487 402 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97
EN		 403#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
404
405 /* Backlight on LVDS connector: J6 */
10fda487 406 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
d67b0d97
EN		 407#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
408};
409
410static iomux_v3_cfg_t const rgb_pads[] = {
411 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
412 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
10fda487
EN		 413 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
414 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
415 MX6_PAD_DI0_PIN4__GPIO4_IO20,
416 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
417 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
418 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
419 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
420 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
421 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
422 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
423 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
424 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
425 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
426 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
427 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
428 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
429 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
430 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
431 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
432 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
433 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
434 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
435 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
436 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
437 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
438 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
439 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
d67b0d97
EN		 440};
441
5ea7f0e3 442static void do_enable_hdmi(struct display_info_t const *dev)
d67b0d97 443{
5ea7f0e3 444 imx_enable_hdmi_phy();
d67b0d97
EN		 445}
446
447static int detect_i2c(struct display_info_t const *dev)
448{
449 return ((0 == i2c_set_bus_num(dev->bus))
450 &&
451 (0 == i2c_probe(dev->addr)));
452}
453
454static void enable_lvds(struct display_info_t const *dev)
455{
456 struct iomuxc *iomux = (struct iomuxc *)
457 IOMUXC_BASE_ADDR;
458 u32 reg = readl(&iomux->gpr[2]);
459 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
460 writel(reg, &iomux->gpr[2]);
461 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
462}
463
464static void enable_rgb(struct display_info_t const *dev)
465{
466 imx_iomux_v3_setup_multiple_pads(
467 rgb_pads,
468 ARRAY_SIZE(rgb_pads));
469 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
470}
471
a47e4495 472struct display_info_t const displays[] = {{
d67b0d97
EN		 473 .bus = -1,
474 .addr = 0,
475 .pixfmt = IPU_PIX_FMT_RGB24,
476 .detect = detect_hdmi,
5ea7f0e3 477 .enable = do_enable_hdmi,
d67b0d97
EN		 478 .mode = {
479 .name = "HDMI",
480 .refresh = 60,
481 .xres = 1024,
482 .yres = 768,
483 .pixclock = 15385,
484 .left_margin = 220,
485 .right_margin = 40,
486 .upper_margin = 21,
487 .lower_margin = 7,
488 .hsync_len = 60,
489 .vsync_len = 10,
490 .sync = FB_SYNC_EXT,
491 .vmode = FB_VMODE_NONINTERLACED
492} }, {
493 .bus = 2,
494 .addr = 0x4,
495 .pixfmt = IPU_PIX_FMT_LVDS666,
496 .detect = detect_i2c,
497 .enable = enable_lvds,
498 .mode = {
499 .name = "Hannstar-XGA",
500 .refresh = 60,
501 .xres = 1024,
502 .yres = 768,
503 .pixclock = 15385,
504 .left_margin = 220,
505 .right_margin = 40,
506 .upper_margin = 21,
507 .lower_margin = 7,
508 .hsync_len = 60,
509 .vsync_len = 10,
510 .sync = FB_SYNC_EXT,
511 .vmode = FB_VMODE_NONINTERLACED
512} }, {
513 .bus = 2,
514 .addr = 0x38,
515 .pixfmt = IPU_PIX_FMT_LVDS666,
516 .detect = detect_i2c,
517 .enable = enable_lvds,
518 .mode = {
519 .name = "wsvga-lvds",
520 .refresh = 60,
521 .xres = 1024,
522 .yres = 600,
523 .pixclock = 15385,
524 .left_margin = 220,
525 .right_margin = 40,
526 .upper_margin = 21,
527 .lower_margin = 7,
528 .hsync_len = 60,
529 .vsync_len = 10,
530 .sync = FB_SYNC_EXT,
531 .vmode = FB_VMODE_NONINTERLACED
532} }, {
533 .bus = 2,
534 .addr = 0x48,
535 .pixfmt = IPU_PIX_FMT_RGB666,
536 .detect = detect_i2c,
537 .enable = enable_rgb,
538 .mode = {
539 .name = "wvga-rgb",
540 .refresh = 57,
541 .xres = 800,
542 .yres = 480,
543 .pixclock = 37037,
544 .left_margin = 40,
545 .right_margin = 60,
546 .upper_margin = 10,
547 .lower_margin = 10,
548 .hsync_len = 20,
549 .vsync_len = 10,
550 .sync = 0,
551 .vmode = FB_VMODE_NONINTERLACED
552} } };
a47e4495 553size_t display_count = ARRAY_SIZE(displays);
d67b0d97 554
c9c86bde
EN		 555int board_cfb_skip(void)
556{
557 return NULL != getenv("novideo");
558}
559
d67b0d97
EN		 560static void setup_display(void)
561{
562 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
d67b0d97 563 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
d67b0d97
EN		 564 int reg;
565
5ea7f0e3
PKS		 566 enable_ipu_clock();
567 imx_setup_hdmi();
d67b0d97
EN		 568 /* Turn on LDB0,IPU,IPU DI0 clocks */
569 reg = __raw_readl(&mxc_ccm->CCGR3);
5ea7f0e3 570 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
d67b0d97
EN		 571 writel(reg, &mxc_ccm->CCGR3);
572
d67b0d97
EN		 573 /* set LDB0, LDB1 clk select to 011/011 */
574 reg = readl(&mxc_ccm->cs2cdr);
575 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
576 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
577 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
578 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
579 writel(reg, &mxc_ccm->cs2cdr);
580
581 reg = readl(&mxc_ccm->cscmr2);
582 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
583 writel(reg, &mxc_ccm->cscmr2);
584
585 reg = readl(&mxc_ccm->chsccdr);
d67b0d97 586 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
5ea7f0e3 587 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
d67b0d97
EN		 588 writel(reg, &mxc_ccm->chsccdr);
589
590 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
591 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
592 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
593 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
594 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
595 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
596 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
597 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
598 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
599 writel(reg, &iomux->gpr[2]);
600
601 reg = readl(&iomux->gpr[3]);
8907c2c5
EN		 602 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
603 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
d67b0d97
EN		 604 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
605 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
606 writel(reg, &iomux->gpr[3]);
607
608 /* backlights off until needed */
609 imx_iomux_v3_setup_multiple_pads(backlight_pads,
610 ARRAY_SIZE(backlight_pads));
611 gpio_direction_input(LVDS_BACKLIGHT_GP);
612 gpio_direction_input(RGB_BACKLIGHT_GP);
613}
614#endif
615
616int board_early_init_f(void)
617{
618 setup_iomux_uart();
619
620 /* Disable wl1271 For Nitrogen6w */
621 gpio_direction_input(WL12XX_WL_IRQ_GP);
622 gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
623 gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
08ce074e 624 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
d67b0d97
EN		 625
626 imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
627 setup_buttons();
628
629#if defined(CONFIG_VIDEO_IPUV3)
630 setup_display();
631#endif
632 return 0;
633}
634
635/*
636 * Do not overwrite the console
637 * Use always serial for U-Boot console
638 */
639int overwrite_console(void)
640{
641 return 1;
642}
643
644int board_init(void)
645{
0a11d6f2 646 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
7132869d
TK		 647
648 clrsetbits_le32(&iomuxc_regs->gpr[1],
649 IOMUXC_GPR1_OTG_ID_MASK,
650 IOMUXC_GPR1_OTG_ID_GPIO1);
651
08ce074e
TK		 652 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
653
d67b0d97
EN		 654 /* address of boot parameters */
655 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
656
657#ifdef CONFIG_MXC_SPI
658 setup_spi();
659#endif
660 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
661 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
662 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
663
664#ifdef CONFIG_CMD_SATA
665 setup_sata();
666#endif
667
668 return 0;
669}
670
671int checkboard(void)
672{
673 if (gpio_get_value(WL12XX_WL_IRQ_GP))
674 puts("Board: Nitrogen6X\n");
675 else
676 puts("Board: SABRE Lite\n");
677
678 return 0;
679}
680
681struct button_key {
682 char const *name;
683 unsigned gpnum;
684 char ident;
685};
686
687static struct button_key const buttons[] = {
688 {"back", IMX_GPIO_NR(2, 2), 'B'},
689 {"home", IMX_GPIO_NR(2, 4), 'H'},
690 {"menu", IMX_GPIO_NR(2, 1), 'M'},
691 {"search", IMX_GPIO_NR(2, 3), 'S'},
692 {"volup", IMX_GPIO_NR(7, 13), 'V'},
693 {"voldown", IMX_GPIO_NR(4, 5), 'v'},
694};
695
696/*
697 * generate a null-terminated string containing the buttons pressed
698 * returns number of keys pressed
699 */
700static int read_keys(char *buf)
701{
702 int i, numpressed = 0;
703 for (i = 0; i < ARRAY_SIZE(buttons); i++) {
704 if (!gpio_get_value(buttons[i].gpnum))
705 buf[numpressed++] = buttons[i].ident;
706 }
707 buf[numpressed] = '\0';
708 return numpressed;
709}
710
711static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
712{
713 char envvalue[ARRAY_SIZE(buttons)+1];
714 int numpressed = read_keys(envvalue);
715 setenv("keybd", envvalue);
716 return numpressed == 0;
717}
718
719U_BOOT_CMD(
720 kbd, 1, 1, do_kbd,
721 "Tests for keypresses, sets 'keybd' environment variable",
722 "Returns 0 (true) to shell if key is pressed."
723);
724
725#ifdef CONFIG_PREBOOT
726static char const kbd_magic_prefix[] = "key_magic";
727static char const kbd_command_prefix[] = "key_cmd";
728
729static void preboot_keys(void)
730{
731 int numpressed;
732 char keypress[ARRAY_SIZE(buttons)+1];
733 numpressed = read_keys(keypress);
734 if (numpressed) {
735 char *kbd_magic_keys = getenv("magic_keys");
736 char *suffix;
737 /*
738 * loop over all magic keys
739 */
740 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
741 char *keys;
742 char magic[sizeof(kbd_magic_prefix) + 1];
743 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
744 keys = getenv(magic);
745 if (keys) {
746 if (!strcmp(keys, keypress))
747 break;
748 }
749 }
750 if (*suffix) {
751 char cmd_name[sizeof(kbd_command_prefix) + 1];
752 char *cmd;
753 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
754 cmd = getenv(cmd_name);
755 if (cmd) {
756 setenv("preboot", cmd);
757 return;
758 }
759 }
760 }
761}
762#endif
763
764#ifdef CONFIG_CMD_BMODE
765static const struct boot_mode board_boot_modes[] = {
766 /* 4 bit bus width */
767 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
768 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
769 {NULL, 0},
770};
771#endif
772
773int misc_init_r(void)
774{
775#ifdef CONFIG_PREBOOT
776 preboot_keys();
777#endif
778
779#ifdef CONFIG_CMD_BMODE
780 add_board_boot_modes(board_boot_modes);
781#endif
782 return 0;
783}
"Das U-Boot" Source Tree