[people/ms/u-boot.git] / board / cerf250 / lowlevel_init.S

/*
 * Most of this taken from Redboot hal_platform_setup.h with cleanup
 *
 * NOTE: I haven't clean this up considerably, just enough to get it
 * running. See hal_platform_setup.h for the source. See
 * board/cradle/lowlevel_init.S for another PXA250 setup that is
 * much cleaner.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>

DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE

/* wait for coprocessor write complete */
   .macro CPWAIT reg
   mrc  p15,0,\reg,c2,c0,0
   mov  \reg,\reg
   sub  pc,pc,#4
   .endm


/*
 *	Memory setup
 */

.globl lowlevel_init
lowlevel_init:

	/* Set up GPIO pins first ----------------------------------------- */

	ldr	r0, =GPSR0
	ldr	r1, =CONFIG_SYS_GPSR0_VAL
	str	r1, [r0]

	ldr	r0, =GPSR1
	ldr	r1, =CONFIG_SYS_GPSR1_VAL
	str	r1, [r0]

	ldr	r0, =GPSR2
	ldr	r1, =CONFIG_SYS_GPSR2_VAL
	str	r1, [r0]

	ldr	r0, =GPCR0
	ldr	r1, =CONFIG_SYS_GPCR0_VAL
	str	r1, [r0]

	ldr	r0, =GPCR1
	ldr	r1, =CONFIG_SYS_GPCR1_VAL
	str	r1, [r0]

	ldr	r0, =GPCR2
	ldr	r1, =CONFIG_SYS_GPCR2_VAL
	str	r1, [r0]

	ldr	r0, =GPDR0
	ldr	r1, =CONFIG_SYS_GPDR0_VAL
	str	r1, [r0]

	ldr	r0, =GPDR1
	ldr	r1, =CONFIG_SYS_GPDR1_VAL
	str	r1, [r0]

	ldr	r0, =GPDR2
	ldr	r1, =CONFIG_SYS_GPDR2_VAL
	str	r1, [r0]

	ldr	r0, =GAFR0_L
	ldr	r1, =CONFIG_SYS_GAFR0_L_VAL
	str	r1, [r0]

	ldr	r0, =GAFR0_U
	ldr	r1, =CONFIG_SYS_GAFR0_U_VAL
	str	r1, [r0]

	ldr	r0, =GAFR1_L
	ldr	r1, =CONFIG_SYS_GAFR1_L_VAL
	str	r1, [r0]

	ldr	r0, =GAFR1_U
	ldr	r1, =CONFIG_SYS_GAFR1_U_VAL
	str	r1, [r0]

	ldr	r0, =GAFR2_L
	ldr	r1, =CONFIG_SYS_GAFR2_L_VAL
	str	r1, [r0]

	ldr	r0, =GAFR2_U
	ldr	r1, =CONFIG_SYS_GAFR2_U_VAL
	str	r1, [r0]

	ldr	r0, =PSSR			/* enable GPIO pins */
	ldr	r1, =CONFIG_SYS_PSSR_VAL
	str	r1, [r0]

	/* ---------------------------------------------------------------- */
	/* Enable memory interface                                          */
	/*                                                                  */
	/* The sequence below is based on the recommended init steps        */
	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	/* Chapter 10.                                                      */
	/* ---------------------------------------------------------------- */

	/* ---------------------------------------------------------------- */
	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
	/*         clocks to settle. Only necessary after hard reset...     */
	/*         FIXME: can be optimized later                            */
	/* ---------------------------------------------------------------- */

	ldr	r3, =OSCR			/* reset the OS Timer Count to zero */
	mov	r2, #0
	str	r2, [r3]
	ldr	r4, =0x300			/* really 0x2E1 is about 200usec,   */
						/* so 0x300 should be plenty        */
1:
	ldr	r2, [r3]
	cmp	r4, r2
	bgt	1b

mem_init:

	ldr	r1, =MEMC_BASE			/* get memory controller base addr. */

	/* ---------------------------------------------------------------- */
	/* Step 2a: Initialize Asynchronous static memory controller        */
	/* ---------------------------------------------------------------- */

	/* MSC registers: timing, bus width, mem type                       */

	/* MSC0: nCS(0,1)                                                   */
	ldr	r2, =CONFIG_SYS_MSC0_VAL
	str	r2, [r1, #MSC0_OFFSET]
	ldr	r2, [r1, #MSC0_OFFSET]		/* read back to ensure      */
						/* that data latches        */
	/* MSC1: nCS(2,3)                                                   */
	ldr	r2, =CONFIG_SYS_MSC1_VAL
	str	r2, [r1, #MSC1_OFFSET]
	ldr	r2, [r1, #MSC1_OFFSET]

	/* MSC2: nCS(4,5)                                                   */
	ldr	r2, =CONFIG_SYS_MSC2_VAL
	str	r2, [r1, #MSC2_OFFSET]
	ldr	r2, [r1, #MSC2_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2b: Initialize Card Interface                               */
	/* ---------------------------------------------------------------- */

	/* MECR: Memory Expansion Card Register                             */
	ldr	r2, =CONFIG_SYS_MECR_VAL
	str	r2, [r1, #MECR_OFFSET]
	ldr	r2, [r1, #MECR_OFFSET]

	/* MCMEM0: Card Interface slot 0 timing                             */
	ldr	r2, =CONFIG_SYS_MCMEM0_VAL
	str	r2, [r1, #MCMEM0_OFFSET]
	ldr	r2, [r1, #MCMEM0_OFFSET]

	/* MCMEM1: Card Interface slot 1 timing                             */
	ldr	r2, =CONFIG_SYS_MCMEM1_VAL
	str	r2, [r1, #MCMEM1_OFFSET]
	ldr	r2, [r1, #MCMEM1_OFFSET]

	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
	ldr	r2, =CONFIG_SYS_MCATT0_VAL
	str	r2, [r1, #MCATT0_OFFSET]
	ldr	r2, [r1, #MCATT0_OFFSET]

	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
	ldr	r2, =CONFIG_SYS_MCATT1_VAL
	str	r2, [r1, #MCATT1_OFFSET]
	ldr	r2, [r1, #MCATT1_OFFSET]

	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
	ldr	r2, =CONFIG_SYS_MCIO0_VAL
	str	r2, [r1, #MCIO0_OFFSET]
	ldr	r2, [r1, #MCIO0_OFFSET]

	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
	ldr	r2, =CONFIG_SYS_MCIO1_VAL
	str	r2, [r1, #MCIO1_OFFSET]
	ldr	r2, [r1, #MCIO1_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
	/* ---------------------------------------------------------------- */


	/* ---------------------------------------------------------------- */
	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
	/* ---------------------------------------------------------------- */

	/* Before accessing MDREFR we need a valid DRI field, so we set     */
	/* this to power on defaults + DRI field, set SDRAM clocks free running */

	ldr	r3, =CONFIG_SYS_MDREFR_VAL
	ldr	r2, =0xFFF
	and	r3, r3,  r2

	ldr	r0, [r1, #MDREFR_OFFSET]
	bic	r0, r0, r2
	bic	r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
	orr	r0, r0, r3

	str	r0, [r1, #MDREFR_OFFSET]	/* write back MDREFR        */


	/* ---------------------------------------------------------------- */
	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	/* ---------------------------------------------------------------- */

	/* Initialize SXCNFG register. Assert the enable bits               */

	/* Write SXMRS to cause an MRS command to all enabled banks of      */
	/* synchronous static memory. Note that SXLCR need not be written   */
	/* at this time.                                                    */

	/* FIXME: we use async mode for now                                 */


	/* ---------------------------------------------------------------- */
	/* Step 4: Initialize SDRAM                                         */
	/* ---------------------------------------------------------------- */

	/* set MDREFR according to user define with exception of a few bits */

	ldr     r4, =CONFIG_SYS_MDREFR_VAL
	ldr	r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
					MDREFR_K2RUN |MDREFR_K2DB2)
	and	r4, r4, r2
	bic	r0, r0, r2
	orr	r0, r0, r4

	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
	ldr     r0, [r1, #MDREFR_OFFSET]

	/* Step 4b: de-assert MDREFR:SLFRSH.                                */

	bic	r0, r0, #(MDREFR_SLFRSH)
	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
	ldr     r0, [r1, #MDREFR_OFFSET]


	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE  */

	ldr     r4, =CONFIG_SYS_MDREFR_VAL
	ldr	r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
			MDREFR_K1FREE | MDREFR_K2FREE)
	and	r4, r4, r2
	orr	r0, r0, r4
	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
	ldr     r0, [r1, #MDREFR_OFFSET]


	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
	/*          configure but not enable each SDRAM partition pair.     */

	ldr	r4, =CONFIG_SYS_MDCNFG_VAL
	bic	r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
	bic	r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
	str     r4, [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
	ldr     r4, [r1, #MDCNFG_OFFSET]


	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
Commit	Line	Data
fabd46ac WD	1	/*
	2	* Most of this taken from Redboot hal_platform_setup.h with cleanup
	3	*
	4	* NOTE: I haven't clean this up considerably, just enough to get it
	5	* running. See hal_platform_setup.h for the source. See
400558b5	6	* board/cradle/lowlevel_init.S for another PXA250 setup that is
fabd46ac WD	7	* much cleaner.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <config.h>
	29	#include <version.h>
	30	#include <asm/arch/pxa-regs.h>
	31
6d0f6bcf	32	DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
fabd46ac WD	33
	34	/* wait for coprocessor write complete */
	35	.macro CPWAIT reg
	36	mrc p15,0,\reg,c2,c0,0
	37	mov \reg,\reg
	38	sub pc,pc,#4
	39	.endm
	40
	41
	42	/*
53677ef1	43	* Memory setup
fabd46ac WD	44	*/
fabd46ac WD	45
400558b5 WD	46	.globl lowlevel_init
400558b5 WD	47	lowlevel_init:
fabd46ac WD	48
	49	/* Set up GPIO pins first ----------------------------------------- */
	50
53677ef1	51	ldr r0, =GPSR0
6d0f6bcf	52	ldr r1, =CONFIG_SYS_GPSR0_VAL
53677ef1	53	str r1, [r0]
fabd46ac	54
53677ef1	55	ldr r0, =GPSR1
6d0f6bcf	56	ldr r1, =CONFIG_SYS_GPSR1_VAL
53677ef1	57	str r1, [r0]
fabd46ac	58
53677ef1	59	ldr r0, =GPSR2
6d0f6bcf	60	ldr r1, =CONFIG_SYS_GPSR2_VAL
53677ef1	61	str r1, [r0]
fabd46ac	62
53677ef1	63	ldr r0, =GPCR0
6d0f6bcf	64	ldr r1, =CONFIG_SYS_GPCR0_VAL
53677ef1	65	str r1, [r0]
fabd46ac	66
53677ef1	67	ldr r0, =GPCR1
6d0f6bcf	68	ldr r1, =CONFIG_SYS_GPCR1_VAL
53677ef1	69	str r1, [r0]
fabd46ac	70
53677ef1	71	ldr r0, =GPCR2
6d0f6bcf	72	ldr r1, =CONFIG_SYS_GPCR2_VAL
53677ef1	73	str r1, [r0]
fabd46ac	74
53677ef1	75	ldr r0, =GPDR0
6d0f6bcf	76	ldr r1, =CONFIG_SYS_GPDR0_VAL
53677ef1	77	str r1, [r0]
fabd46ac	78
53677ef1	79	ldr r0, =GPDR1
6d0f6bcf	80	ldr r1, =CONFIG_SYS_GPDR1_VAL
53677ef1	81	str r1, [r0]
fabd46ac	82
53677ef1	83	ldr r0, =GPDR2
6d0f6bcf	84	ldr r1, =CONFIG_SYS_GPDR2_VAL
53677ef1	85	str r1, [r0]
fabd46ac	86
53677ef1	87	ldr r0, =GAFR0_L
6d0f6bcf	88	ldr r1, =CONFIG_SYS_GAFR0_L_VAL
53677ef1	89	str r1, [r0]
fabd46ac	90
53677ef1	91	ldr r0, =GAFR0_U
6d0f6bcf	92	ldr r1, =CONFIG_SYS_GAFR0_U_VAL
53677ef1	93	str r1, [r0]
fabd46ac	94
53677ef1	95	ldr r0, =GAFR1_L
6d0f6bcf	96	ldr r1, =CONFIG_SYS_GAFR1_L_VAL
53677ef1	97	str r1, [r0]
fabd46ac	98
53677ef1	99	ldr r0, =GAFR1_U
6d0f6bcf	100	ldr r1, =CONFIG_SYS_GAFR1_U_VAL
53677ef1	101	str r1, [r0]
fabd46ac	102
53677ef1	103	ldr r0, =GAFR2_L
6d0f6bcf	104	ldr r1, =CONFIG_SYS_GAFR2_L_VAL
53677ef1	105	str r1, [r0]
fabd46ac	106
53677ef1	107	ldr r0, =GAFR2_U
6d0f6bcf	108	ldr r1, =CONFIG_SYS_GAFR2_U_VAL
53677ef1	109	str r1, [r0]
fabd46ac	110
53677ef1	111	ldr r0, =PSSR /* enable GPIO pins */
6d0f6bcf	112	ldr r1, =CONFIG_SYS_PSSR_VAL
53677ef1	113	str r1, [r0]
fabd46ac WD	114
	115	/* ---------------------------------------------------------------- */
	116	/* Enable memory interface */
	117	/* */
	118	/* The sequence below is based on the recommended init steps */
	119	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	120	/* Chapter 10. */
	121	/* ---------------------------------------------------------------- */
	122
	123	/* ---------------------------------------------------------------- */
	124	/* Step 1: Wait for at least 200 microsedonds to allow internal */
	125	/* clocks to settle. Only necessary after hard reset... */
	126	/* FIXME: can be optimized later */
	127	/* ---------------------------------------------------------------- */
	128
53677ef1 WD	129	ldr r3, =OSCR /* reset the OS Timer Count to zero */
	130	mov r2, #0
	131	str r2, [r3]
	132	ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
	133	/* so 0x300 should be plenty */
fabd46ac	134	1:
53677ef1 WD	135	ldr r2, [r3]
	136	cmp r4, r2
	137	bgt 1b
fabd46ac WD	138
	139	mem_init:
	140
53677ef1	141	ldr r1, =MEMC_BASE /* get memory controller base addr. */
fabd46ac WD	142
	143	/* ---------------------------------------------------------------- */
	144	/* Step 2a: Initialize Asynchronous static memory controller */
	145	/* ---------------------------------------------------------------- */
	146
	147	/* MSC registers: timing, bus width, mem type */
	148
	149	/* MSC0: nCS(0,1) */
6d0f6bcf	150	ldr r2, =CONFIG_SYS_MSC0_VAL
53677ef1 WD	151	str r2, [r1, #MSC0_OFFSET]
53677ef1 WD	152	ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
fabd46ac WD	153	/* that data latches */
fabd46ac WD	154	/* MSC1: nCS(2,3) */
6d0f6bcf	155	ldr r2, =CONFIG_SYS_MSC1_VAL
53677ef1 WD	156	str r2, [r1, #MSC1_OFFSET]
53677ef1 WD	157	ldr r2, [r1, #MSC1_OFFSET]
fabd46ac WD	158
fabd46ac WD	159	/* MSC2: nCS(4,5) */
6d0f6bcf	160	ldr r2, =CONFIG_SYS_MSC2_VAL
53677ef1 WD	161	str r2, [r1, #MSC2_OFFSET]
53677ef1 WD	162	ldr r2, [r1, #MSC2_OFFSET]
fabd46ac WD	163
	164	/* ---------------------------------------------------------------- */
	165	/* Step 2b: Initialize Card Interface */
	166	/* ---------------------------------------------------------------- */
	167
	168	/* MECR: Memory Expansion Card Register */
6d0f6bcf	169	ldr r2, =CONFIG_SYS_MECR_VAL
53677ef1 WD	170	str r2, [r1, #MECR_OFFSET]
53677ef1 WD	171	ldr r2, [r1, #MECR_OFFSET]
fabd46ac WD	172
fabd46ac WD	173	/* MCMEM0: Card Interface slot 0 timing */
6d0f6bcf	174	ldr r2, =CONFIG_SYS_MCMEM0_VAL
53677ef1 WD	175	str r2, [r1, #MCMEM0_OFFSET]
53677ef1 WD	176	ldr r2, [r1, #MCMEM0_OFFSET]
fabd46ac WD	177
fabd46ac WD	178	/* MCMEM1: Card Interface slot 1 timing */
6d0f6bcf	179	ldr r2, =CONFIG_SYS_MCMEM1_VAL
53677ef1 WD	180	str r2, [r1, #MCMEM1_OFFSET]
53677ef1 WD	181	ldr r2, [r1, #MCMEM1_OFFSET]
fabd46ac WD	182
fabd46ac WD	183	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
6d0f6bcf	184	ldr r2, =CONFIG_SYS_MCATT0_VAL
53677ef1 WD	185	str r2, [r1, #MCATT0_OFFSET]
53677ef1 WD	186	ldr r2, [r1, #MCATT0_OFFSET]
fabd46ac WD	187
fabd46ac WD	188	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
6d0f6bcf	189	ldr r2, =CONFIG_SYS_MCATT1_VAL
53677ef1 WD	190	str r2, [r1, #MCATT1_OFFSET]
53677ef1 WD	191	ldr r2, [r1, #MCATT1_OFFSET]
fabd46ac WD	192
fabd46ac WD	193	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
6d0f6bcf	194	ldr r2, =CONFIG_SYS_MCIO0_VAL
53677ef1 WD	195	str r2, [r1, #MCIO0_OFFSET]
53677ef1 WD	196	ldr r2, [r1, #MCIO0_OFFSET]
fabd46ac WD	197
fabd46ac WD	198	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
6d0f6bcf	199	ldr r2, =CONFIG_SYS_MCIO1_VAL
53677ef1 WD	200	str r2, [r1, #MCIO1_OFFSET]
53677ef1 WD	201	ldr r2, [r1, #MCIO1_OFFSET]
fabd46ac WD	202
	203	/* ---------------------------------------------------------------- */
	204	/* Step 2c: Write FLYCNFG FIXME: what's that??? */
	205	/* ---------------------------------------------------------------- */
	206
	207
	208	/* ---------------------------------------------------------------- */
	209	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
	210	/* ---------------------------------------------------------------- */
	211
	212	/* Before accessing MDREFR we need a valid DRI field, so we set */
	213	/* this to power on defaults + DRI field, set SDRAM clocks free running */
	214
6d0f6bcf	215	ldr r3, =CONFIG_SYS_MDREFR_VAL
53677ef1 WD	216	ldr r2, =0xFFF
53677ef1 WD	217	and r3, r3, r2
fabd46ac	218
53677ef1 WD	219	ldr r0, [r1, #MDREFR_OFFSET]
	220	bic r0, r0, r2
	221	bic r0, r0, #(MDREFR_K0FREE\|MDREFR_K1FREE\|MDREFR_K2FREE)
	222	orr r0, r0, r3
fabd46ac	223
53677ef1	224	str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
fabd46ac WD	225
	226
	227	/* ---------------------------------------------------------------- */
	228	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	229	/* ---------------------------------------------------------------- */
	230
	231	/* Initialize SXCNFG register. Assert the enable bits */
	232
	233	/* Write SXMRS to cause an MRS command to all enabled banks of */
	234	/* synchronous static memory. Note that SXLCR need not be written */
	235	/* at this time. */
	236
	237	/* FIXME: we use async mode for now */
	238
	239
	240	/* ---------------------------------------------------------------- */
	241	/* Step 4: Initialize SDRAM */
	242	/* ---------------------------------------------------------------- */
	243
	244	/* set MDREFR according to user define with exception of a few bits */
	245
6d0f6bcf	246	ldr r4, =CONFIG_SYS_MDREFR_VAL
53677ef1	247	ldr r2, =(MDREFR_K0RUN\|MDREFR_K0DB2\|MDREFR_K1RUN\|MDREFR_K1DB2\|\
fabd46ac	248	MDREFR_K2RUN \|MDREFR_K2DB2)
53677ef1 WD	249	and r4, r4, r2
	250	bic r0, r0, r2
	251	orr r0, r0, r4
fabd46ac WD	252
	253	str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
	254	ldr r0, [r1, #MDREFR_OFFSET]
	255
	256	/* Step 4b: de-assert MDREFR:SLFRSH. */
	257
53677ef1	258	bic r0, r0, #(MDREFR_SLFRSH)
fabd46ac WD	259	str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
	260	ldr r0, [r1, #MDREFR_OFFSET]
	261
	262
	263	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */
	264
6d0f6bcf	265	ldr r4, =CONFIG_SYS_MDREFR_VAL
53677ef1 WD	266	ldr r2, =(MDREFR_E0PIN\|MDREFR_E1PIN\|MDREFR_K0FREE\| \
	267	MDREFR_K1FREE \| MDREFR_K2FREE)
	268	and r4, r4, r2
	269	orr r0, r0, r4
fabd46ac WD	270	str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
	271	ldr r0, [r1, #MDREFR_OFFSET]
	272
	273
	274	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
	275	/* configure but not enable each SDRAM partition pair. */
	276
6d0f6bcf	277	ldr r4, =CONFIG_SYS_MDCNFG_VAL
53677ef1 WD	278	bic r4, r4, #(MDCNFG_DE0\|MDCNFG_DE1)
53677ef1 WD	279	bic r4, r4, #(MDCNFG_DE2\|MDCNFG_DE3)
fabd46ac WD	280	str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
	281	ldr r4, [r1, #MDCNFG_OFFSET]
	282
	283
	284	/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
	285