[thirdparty/u-boot.git] / board / cloudengines / pogo_e02 / kwbimage.cfg

# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2012
# David Purdy <david.c.purdy@gmail.com>
#
# Based on Kirkwood support:
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#

# Boot Media configurations
BOOT_FROM	nand
NAND_ECC_MODE	default
NAND_PAGE_SIZE	0x0800

# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed

# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xffd100e0 0x1b1b1b9b

#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xffd01400 0x43000c30	# DDR Configuration register
# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01

DATA 0xffd01404 0x37543000	# DDR Controller Control Low
# bit 4:    0=addr/cmd in smame cycle
# bit 5:    0=clk is driven during self refresh, we don't care for APX
# bit 6:    0=use recommended falling edge of clk for addr/cmd
# bit14:    0=input buffer always powered up
# bit18:    1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31:    0=no additional STARTBURST delay

DATA 0xffd01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
# bit3-0:   TRAS lsbs
# bit7-4:   TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20:    TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP

DATA 0xffd0140c 0x00000a33	#  DDR Timing (High)
# bit6-0:   TRFC
# bit8-7:   TR2R
# bit10-9:  TR2W
# bit12-11: TW2W
# bit31-13: zero required

DATA 0xffd01410 0x000000cc	#  DDR Address Control
# bit1-0:   00, Cs0width=x8
# bit3-2:   11, Cs0size=1Gb
# bit5-4:   00, Cs1width=x8
# bit7-6:   11, Cs1size=1Gb
# bit9-8:   00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16:    0,  Cs0AddrSel
# bit17:    0,  Cs1AddrSel
# bit18:    0,  Cs2AddrSel
# bit19:    0,  Cs3AddrSel
# bit31-20: 0 required

DATA 0xffd01414 0x00000000	#  DDR Open Pages Control
# bit0:    0,  OpenPage enabled
# bit31-1: 0 required

DATA 0xffd01418 0x00000000	#  DDR Operation
# bit3-0:   0x0, DDR cmd
# bit31-4:  0 required

DATA 0xffd0141c 0x00000c52	#  DDR Mode
# bit2-0:   2, BurstLen=2 required
# bit3:     0, BurstType=0 required
# bit6-4:   4, CL=5
# bit7:     0, TestMode=0 normal
# bit8:     0, DLL reset=0 normal
# bit11-9:  6, auto-precharge write recovery ????????????
# bit12:    0, PD must be zero
# bit31-13: 0 required

DATA 0xffd01420 0x00000040	#  DDR Extended Mode
# bit0:    0,  DDR DLL enabled
# bit1:    0,  DDR drive strenght normal
# bit2:    0,  DDR ODT control lsd (disabled)
# bit5-3:  000, required
# bit6:    1,  DDR ODT control msb, (disabled)
# bit9-7:  000, required
# bit10:   0,  differential DQS enabled
# bit11:   0, required
# bit12:   0, DDR output buffer enabled
# bit31-13: 0 required

DATA 0xffd01424 0x0000f17f	#  DDR Controller Control High
# bit2-0:  111, required
# bit3  :  1  , MBUS Burst Chop disabled
# bit6-4:  111, required
# bit7  :  0
# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9  :  0  , no half clock cycle addition to dataout
# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0    required

DATA 0xffd01428 0x00085520	# DDR2 ODT Read Timing (default values)
DATA 0xffd0147c 0x00008552	# DDR2 ODT Write Timing (default values)

DATA 0xffd01500 0x00000000	# CS[0]n Base address to 0x0
DATA 0xffd01504 0x0ffffff1	# CS[0]n Size
# bit0:    1,  Window enabled
# bit1:    0,  Write Protect disabled
# bit3-2:  00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x0F, Size (i.e. 256MB)

DATA 0xffd01508 0x10000000	# CS[1]n Base address to 256Mb
DATA 0xffd0150c 0x00000000	# CS[2]n Size, window disabled

DATA 0xffd01514 0x00000000	# CS[2]n Size, window disabled
DATA 0xffd0151c 0x00000000	# CS[3]n Size, window disabled

DATA 0xffd01494 0x00030000	#  DDR ODT Control (Low)
# bit3-0:  2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
# bit7-4:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0

DATA 0xffd01498 0x00000000	#  DDR ODT Control (High)
# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
# bit3-2:  01, ODT1 active NEVER!
# bit31-4: zero, required

DATA 0xffd0149c 0x0000e803	# CPU ODT Control
DATA 0xffd01480 0x00000001	# DDR Initialization Control
#bit0=1, enable DDR init upon this register write

# End of Header extension
DATA 0x0 0x0
Commit	Line	Data
83d290c5	1	# SPDX-License-Identifier: GPL-2.0+
1d0f5fa1 DP	2	#
	3	# Copyright (C) 2012
	4	# David Purdy <david.c.purdy@gmail.com>
	5	#
	6	# Based on Kirkwood support:
	7	# (C) Copyright 2009
	8	# Marvell Semiconductor <www.marvell.com>
	9	# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
b1e6c4c3	10	# Refer doc/README.kwbimage for more details about how-to configure
1d0f5fa1 DP	11	# and create kirkwood boot image
	12	#
	13
	14	# Boot Media configurations
	15	BOOT_FROM nand
	16	NAND_ECC_MODE default
	17	NAND_PAGE_SIZE 0x0800
	18
	19	# SOC registers configuration using bootrom header extension
	20	# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
	21
	22	# Configure RGMII-0 interface pad voltage to 1.8V
	23	DATA 0xffd100e0 0x1b1b1b9b
	24
	25	#Dram initalization for SINGLE x16 CL=5 @ 400MHz
	26	DATA 0xffd01400 0x43000c30 # DDR Configuration register
	27	# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
	28	# bit23-14: zero
	29	# bit24: 1= enable exit self refresh mode on DDR access
	30	# bit25: 1 required
	31	# bit29-26: zero
	32	# bit31-30: 01
	33
	34	DATA 0xffd01404 0x37543000 # DDR Controller Control Low
	35	# bit 4: 0=addr/cmd in smame cycle
	36	# bit 5: 0=clk is driven during self refresh, we don't care for APX
	37	# bit 6: 0=use recommended falling edge of clk for addr/cmd
	38	# bit14: 0=input buffer always powered up
	39	# bit18: 1=cpu lock transaction enabled
	40	# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
	41	# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
	42	# bit30-28: 3 required
	43	# bit31: 0=no additional STARTBURST delay
	44
	45	DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
	46	# bit3-0: TRAS lsbs
	47	# bit7-4: TRCD
	48	# bit11- 8: TRP
	49	# bit15-12: TWR
	50	# bit19-16: TWTR
	51	# bit20: TRAS msb
	52	# bit23-21: 0x0
	53	# bit27-24: TRRD
	54	# bit31-28: TRTP
	55
	56	DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
	57	# bit6-0: TRFC
	58	# bit8-7: TR2R
	59	# bit10-9: TR2W
	60	# bit12-11: TW2W
	61	# bit31-13: zero required
	62
	63	DATA 0xffd01410 0x000000cc # DDR Address Control
	64	# bit1-0: 00, Cs0width=x8
	65	# bit3-2: 11, Cs0size=1Gb
	66	# bit5-4: 00, Cs1width=x8
	67	# bit7-6: 11, Cs1size=1Gb
	68	# bit9-8: 00, Cs2width=nonexistent
	69	# bit11-10: 00, Cs2size =nonexistent
	70	# bit13-12: 00, Cs3width=nonexistent
	71	# bit15-14: 00, Cs3size =nonexistent
	72	# bit16: 0, Cs0AddrSel
	73	# bit17: 0, Cs1AddrSel
	74	# bit18: 0, Cs2AddrSel
75	# bit19: 0, Cs3AddrSel
76	# bit31-20: 0 required
77
78	DATA 0xffd01414 0x00000000 # DDR Open Pages Control
79	# bit0: 0, OpenPage enabled
80	# bit31-1: 0 required
81
82	DATA 0xffd01418 0x00000000 # DDR Operation
83	# bit3-0: 0x0, DDR cmd
84	# bit31-4: 0 required
85
86	DATA 0xffd0141c 0x00000c52 # DDR Mode
87	# bit2-0: 2, BurstLen=2 required
88	# bit3: 0, BurstType=0 required
89	# bit6-4: 4, CL=5
90	# bit7: 0, TestMode=0 normal
91	# bit8: 0, DLL reset=0 normal
92	# bit11-9: 6, auto-precharge write recovery ????????????
93	# bit12: 0, PD must be zero
94	# bit31-13: 0 required
95
96	DATA 0xffd01420 0x00000040 # DDR Extended Mode
97	# bit0: 0, DDR DLL enabled
98	# bit1: 0, DDR drive strenght normal
99	# bit2: 0, DDR ODT control lsd (disabled)
100	# bit5-3: 000, required
101	# bit6: 1, DDR ODT control msb, (disabled)
102	# bit9-7: 000, required
103	# bit10: 0, differential DQS enabled
104	# bit11: 0, required
105	# bit12: 0, DDR output buffer enabled
106	# bit31-13: 0 required
107
108	DATA 0xffd01424 0x0000f17f # DDR Controller Control High
109	# bit2-0: 111, required
110	# bit3 : 1 , MBUS Burst Chop disabled
111	# bit6-4: 111, required
112	# bit7 : 0
113	# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
114	# bit9 : 0 , no half clock cycle addition to dataout
115	# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
116	# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
117	# bit15-12: 1111 required
118	# bit31-16: 0 required
119
120	DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
121	DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
122
123	DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
124	DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
125	# bit0: 1, Window enabled
126	# bit1: 0, Write Protect disabled
127	# bit3-2: 00, CS0 hit selected
128	# bit23-4: ones, required
129	# bit31-24: 0x0F, Size (i.e. 256MB)
130
131	DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb
132	DATA 0xffd0150c 0x00000000 # CS[2]n Size, window disabled
133
134	DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
135	DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
136
137	DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
138	# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
139	# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
140	# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
141	# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
142
143	DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
144	# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
145	# bit3-2: 01, ODT1 active NEVER!
146	# bit31-4: zero, required
147
148	DATA 0xffd0149c 0x0000e803 # CPU ODT Control
149	DATA 0xffd01480 0x00000001 # DDR Initialization Control
150	#bit0=1, enable DDR init upon this register write
151
152	# End of Header extension
153	DATA 0x0 0x0