]>
Commit | Line | Data |
---|---|---|
86b116b1 BS |
1 | /* |
2 | * (C) Copyright 2003-2007 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. | |
7 | * | |
8 | * (C) Copyright 2004-2005 | |
9 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
10 | * | |
11 | * Adapted to U-Boot 1.2 by: | |
12 | * Bartlomiej Sieka <tur@semihalf.com>: | |
13 | * - HW ID readout from EEPROM | |
14 | * - module detection | |
15 | * Grzegorz Bernacki <gjb@semihalf.com>: | |
16 | * - run-time SDRAM controller configuration | |
17 | * - LIBFDT support | |
18 | * | |
19 | * See file CREDITS for list of people who contributed to this | |
20 | * project. | |
21 | * | |
22 | * This program is free software; you can redistribute it and/or | |
23 | * modify it under the terms of the GNU General Public License as | |
24 | * published by the Free Software Foundation; either version 2 of | |
25 | * the License, or (at your option) any later version. | |
26 | * | |
27 | * This program is distributed in the hope that it will be useful, | |
28 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
29 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
30 | * GNU General Public License for more details. | |
31 | * | |
32 | * You should have received a copy of the GNU General Public License | |
33 | * along with this program; if not, write to the Free Software | |
34 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
35 | * MA 02111-1307 USA | |
36 | */ | |
37 | ||
38 | #include <common.h> | |
39 | #include <mpc5xxx.h> | |
40 | #include <pci.h> | |
41 | #include <asm/processor.h> | |
42 | #include <i2c.h> | |
43 | #include <linux/ctype.h> | |
44 | ||
45 | #ifdef CONFIG_OF_LIBFDT | |
46 | #include <libfdt.h> | |
86b116b1 BS |
47 | #include <fdt_support.h> |
48 | #endif /* CONFIG_OF_LIBFDT */ | |
49 | ||
50 | ||
51 | #include "cm5200.h" | |
52 | #include "fwupdate.h" | |
53 | ||
54 | DECLARE_GLOBAL_DATA_PTR; | |
55 | ||
56 | static hw_id_t hw_id; | |
57 | ||
58 | ||
6d0f6bcf | 59 | #ifndef CONFIG_SYS_RAMBOOT |
86b116b1 BS |
60 | /* |
61 | * Helper function to initialize SDRAM controller. | |
62 | */ | |
63 | static void sdram_start(int hi_addr, mem_conf_t *mem_conf) | |
64 | { | |
65 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | |
66 | ||
67 | /* unlock mode register */ | |
68 | *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 | | |
69 | hi_addr_bit; | |
70 | ||
71 | /* precharge all banks */ | |
72 | *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 | | |
73 | hi_addr_bit; | |
74 | ||
75 | /* auto refresh */ | |
76 | *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 | | |
77 | hi_addr_bit; | |
78 | ||
79 | /* auto refresh, second time */ | |
80 | *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 | | |
81 | hi_addr_bit; | |
82 | ||
83 | /* set mode register */ | |
84 | *(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode; | |
85 | ||
86 | /* normal operation */ | |
87 | *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit; | |
88 | } | |
6d0f6bcf | 89 | #endif /* CONFIG_SYS_RAMBOOT */ |
86b116b1 BS |
90 | |
91 | ||
92 | /* | |
93 | * Retrieve memory configuration for a given module. board_type is the index | |
94 | * in hw_id_list[] corresponding to the module we are executing on; we return | |
95 | * SDRAM controller settings approprate for this module. | |
96 | */ | |
97 | static mem_conf_t* get_mem_config(int board_type) | |
98 | { | |
99 | switch(board_type){ | |
100 | case CM1_QA: | |
101 | return memory_config[0]; | |
102 | case CM11_QA: | |
103 | case CMU1_QA: | |
104 | return memory_config[1]; | |
105 | default: | |
106 | printf("ERROR: Unknown module, using a default SDRAM " | |
107 | "configuration - things may not work!!!.\n"); | |
108 | return memory_config[0]; | |
109 | } | |
110 | } | |
111 | ||
112 | ||
113 | /* | |
114 | * Initalize SDRAM - configure SDRAM controller, detect memory size. | |
115 | */ | |
9973e3c6 | 116 | phys_size_t initdram(int board_type) |
86b116b1 BS |
117 | { |
118 | ulong dramsize = 0; | |
6d0f6bcf | 119 | #ifndef CONFIG_SYS_RAMBOOT |
86b116b1 BS |
120 | ulong test1, test2; |
121 | mem_conf_t *mem_conf; | |
122 | ||
123 | mem_conf = get_mem_config(board_type); | |
be5d72d1 | 124 | |
86b116b1 BS |
125 | /* configure SDRAM start/end for detection */ |
126 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ | |
127 | ||
128 | /* setup config registers */ | |
129 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1; | |
130 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2; | |
131 | ||
132 | sdram_start(0, mem_conf); | |
6d0f6bcf | 133 | test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); |
86b116b1 | 134 | sdram_start(1, mem_conf); |
6d0f6bcf | 135 | test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); |
86b116b1 BS |
136 | if (test1 > test2) { |
137 | sdram_start(0, mem_conf); | |
138 | dramsize = test1; | |
139 | } else | |
140 | dramsize = test2; | |
141 | ||
142 | /* memory smaller than 1MB is impossible */ | |
143 | if (dramsize < (1 << 20)) | |
144 | dramsize = 0; | |
145 | ||
146 | /* set SDRAM CS0 size according to the amount of RAM found */ | |
147 | if (dramsize > 0) { | |
148 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + | |
149 | __builtin_ffs(dramsize >> 20) - 1; | |
150 | } else | |
151 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ | |
6d0f6bcf | 152 | #else /* CONFIG_SYS_RAMBOOT */ |
86b116b1 BS |
153 | /* retrieve size of memory connected to SDRAM CS0 */ |
154 | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; | |
155 | if (dramsize >= 0x13) | |
156 | dramsize = (1 << (dramsize - 0x13)) << 20; | |
157 | else | |
158 | dramsize = 0; | |
6d0f6bcf | 159 | #endif /* !CONFIG_SYS_RAMBOOT */ |
86b116b1 BS |
160 | |
161 | /* | |
162 | * On MPC5200B we need to set the special configuration delay in the | |
163 | * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of | |
164 | * the MPC5200B User's Manual. | |
165 | */ | |
166 | *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; | |
167 | __asm__ volatile ("sync"); | |
168 | ||
169 | return dramsize; | |
170 | } | |
171 | ||
172 | ||
173 | /* | |
174 | * Read module hardware identification data from the I2C EEPROM. | |
175 | */ | |
176 | static void read_hw_id(hw_id_t hw_id) | |
177 | { | |
178 | int i; | |
179 | for (i = 0; i < HW_ID_ELEM_COUNT; ++i) | |
6d0f6bcf | 180 | if (i2c_read(CONFIG_SYS_I2C_EEPROM, |
86b116b1 BS |
181 | hw_id_format[i].offset, |
182 | 2, | |
183 | (uchar *)&hw_id[i][0], | |
184 | hw_id_format[i].length) != 0) | |
185 | printf("ERROR: can't read HW ID from EEPROM\n"); | |
186 | } | |
187 | ||
188 | ||
189 | /* | |
190 | * Identify module we are running on, set gd->board_type to the index in | |
191 | * hw_id_list[] corresponding to the module identifed, or to | |
192 | * CM5200_UNKNOWN_MODULE if we can't identify the module. | |
193 | */ | |
194 | static void identify_module(hw_id_t hw_id) | |
195 | { | |
196 | int i, j, element; | |
197 | char match; | |
198 | gd->board_type = CM5200_UNKNOWN_MODULE; | |
199 | for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) { | |
200 | match = 1; | |
201 | for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) { | |
202 | element = hw_id_identify[j]; | |
203 | if (strncmp(hw_id_list[i][element], | |
204 | &hw_id[element][0], | |
205 | hw_id_format[element].length) != 0) { | |
206 | match = 0; | |
207 | break; | |
208 | } | |
209 | } | |
210 | if (match) { | |
211 | gd->board_type = i; | |
212 | break; | |
213 | } | |
214 | } | |
215 | } | |
216 | ||
217 | ||
218 | /* | |
219 | * Compose string with module name. | |
220 | * buf is assumed to have enough space, and be null-terminated. | |
221 | */ | |
222 | static void compose_module_name(hw_id_t hw_id, char *buf) | |
223 | { | |
224 | char tmp[MODULE_NAME_MAXLEN]; | |
225 | strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length); | |
226 | strncat(buf, ".", 1); | |
227 | strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length); | |
228 | strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length); | |
229 | strncat(buf, " (", 2); | |
230 | strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0], | |
231 | hw_id_format[IDENTIFICATION_NUMBER].length); | |
232 | sprintf(tmp, " / %u.%u)", | |
233 | hw_id[MAJOR_SW_VERSION][0], | |
234 | hw_id[MINOR_SW_VERSION][0]); | |
235 | strcat(buf, tmp); | |
236 | } | |
237 | ||
238 | ||
239 | /* | |
240 | * Compose string with hostname. | |
241 | * buf is assumed to have enough space, and be null-terminated. | |
242 | */ | |
243 | static void compose_hostname(hw_id_t hw_id, char *buf) | |
244 | { | |
245 | char *p; | |
246 | strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length); | |
247 | strncat(buf, "_", 1); | |
248 | strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length); | |
249 | strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length); | |
250 | for (p = buf; *p; ++p) | |
251 | *p = tolower(*p); | |
252 | ||
253 | } | |
254 | ||
255 | ||
256 | #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) | |
257 | /* | |
258 | * Update 'model' and 'memory' properties in the blob according to the module | |
259 | * that we are running on. | |
260 | */ | |
261 | static void ft_blob_update(void *blob, bd_t *bd) | |
262 | { | |
263 | int len, ret, nodeoffset = 0; | |
264 | char module_name[MODULE_NAME_MAXLEN] = {0}; | |
86b116b1 BS |
265 | |
266 | compose_module_name(hw_id, module_name); | |
267 | len = strlen(module_name) + 1; | |
268 | ||
269 | ret = fdt_setprop(blob, nodeoffset, "model", module_name, len); | |
270 | if (ret < 0) | |
271 | printf("ft_blob_update(): cannot set /model property err:%s\n", | |
272 | fdt_strerror(ret)); | |
86b116b1 BS |
273 | } |
274 | #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ | |
275 | ||
276 | ||
277 | /* | |
278 | * Read HW ID from I2C EEPROM and detect the modue we are running on. Note | |
279 | * that we need to use local variable for readout, because global data is not | |
280 | * writable yet (and we'll have to redo the readout later on). | |
281 | */ | |
282 | int checkboard(void) | |
283 | { | |
284 | hw_id_t hw_id_tmp; | |
285 | char module_name_tmp[MODULE_NAME_MAXLEN] = ""; | |
286 | ||
be5d72d1 | 287 | /* |
86b116b1 BS |
288 | * We need I2C to access HW ID data from EEPROM, so we call i2c_init() |
289 | * here despite the fact that it will be called again later on. We | |
290 | * also use a little trick to silence I2C-related output. | |
291 | */ | |
292 | gd->flags |= GD_FLG_SILENT; | |
6d0f6bcf | 293 | i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
86b116b1 BS |
294 | gd->flags &= ~GD_FLG_SILENT; |
295 | ||
296 | read_hw_id(hw_id_tmp); | |
297 | identify_module(hw_id_tmp); /* this sets gd->board_type */ | |
298 | compose_module_name(hw_id_tmp, module_name_tmp); | |
299 | ||
300 | if (gd->board_type != CM5200_UNKNOWN_MODULE) | |
301 | printf("Board: %s\n", module_name_tmp); | |
302 | else | |
303 | printf("Board: unrecognized cm5200 module (%s)\n", | |
304 | module_name_tmp); | |
be5d72d1 | 305 | |
86b116b1 BS |
306 | return 0; |
307 | } | |
308 | ||
309 | ||
310 | int board_early_init_r(void) | |
311 | { | |
312 | /* | |
313 | * Now, when we are in RAM, enable flash write access for detection | |
314 | * process. Note that CS_BOOT cannot be cleared when executing in | |
315 | * flash. | |
316 | */ | |
317 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ | |
318 | ||
319 | /* Now that we can write to global data, read HW ID again. */ | |
320 | read_hw_id(hw_id); | |
321 | return 0; | |
322 | } | |
323 | ||
324 | ||
86b116b1 BS |
325 | #ifdef CONFIG_MISC_INIT_R |
326 | int misc_init_r(void) | |
327 | { | |
ea818dbb | 328 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) |
86b116b1 BS |
329 | uchar buf[6]; |
330 | char str[18]; | |
331 | char hostname[MODULE_NAME_MAXLEN]; | |
332 | ||
333 | /* Read ethaddr from EEPROM */ | |
6d0f6bcf | 334 | if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) { |
86b116b1 BS |
335 | sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", |
336 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); | |
337 | /* Check if MAC addr is owned by Schindler */ | |
338 | if (strstr(str, "00:06:C3") != str) | |
339 | printf(LOG_PREFIX "Warning - Illegal MAC address (%s)" | |
340 | " in EEPROM.\n", str); | |
341 | else { | |
342 | printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n", | |
343 | str); | |
344 | setenv("ethaddr", str); | |
345 | } | |
346 | } else { | |
347 | printf(LOG_PREFIX "Warning - Unable to read MAC from I2C" | |
6d0f6bcf | 348 | " device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM, |
86b116b1 BS |
349 | CONFIG_MAC_OFFSET); |
350 | } | |
ea818dbb | 351 | #endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) */ |
86b116b1 BS |
352 | if (!getenv("ethaddr")) |
353 | printf(LOG_PREFIX "MAC address not set, networking is not " | |
354 | "operational\n"); | |
355 | ||
356 | /* set the hostname appropriate to the module we're running on */ | |
92869195 | 357 | hostname[0] = 0x00; |
86b116b1 BS |
358 | compose_hostname(hw_id, hostname); |
359 | setenv("hostname", hostname); | |
360 | ||
361 | return 0; | |
362 | } | |
363 | #endif /* CONFIG_MISC_INIT_R */ | |
364 | ||
365 | ||
366 | #ifdef CONFIG_LAST_STAGE_INIT | |
367 | int last_stage_init(void) | |
368 | { | |
369 | #ifdef CONFIG_USB_STORAGE | |
370 | cm5200_fwupdate(); | |
371 | #endif /* CONFIG_USB_STORAGE */ | |
372 | return 0; | |
373 | } | |
374 | #endif /* CONFIG_LAST_STAGE_INIT */ | |
375 | ||
376 | ||
377 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | |
378 | void ft_board_setup(void *blob, bd_t *bd) | |
379 | { | |
380 | ft_cpu_setup(blob, bd); | |
381 | ft_blob_update(blob, bd); | |
382 | } | |
383 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |