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1 | /* |
2 | * (C) Copyright 2007 DENX Software Engineering | |
3 | * | |
4 | * Author: Bartlomiej Sieka <tur@semihalf.com> | |
5 | * Author: Grzegorz Bernacki <gjb@semihalf.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
86b116b1 BS |
8 | */ |
9 | ||
10 | #ifndef _CM5200_H | |
11 | #define _CM5200_H | |
12 | ||
13 | ||
14 | /* | |
15 | * Definitions and declarations for the modules of the cm5200 platform. Mostly | |
16 | * related to reading the hardware identification data (HW ID) from the I2C | |
17 | * EEPROM, detection of the particular module we are executing on, and | |
18 | * appropriate SDRAM controller initialization. | |
19 | */ | |
20 | ||
21 | ||
22 | #define CM5200_UNKNOWN_MODULE 0xffffffff | |
23 | ||
24 | enum { | |
25 | DEVICE_NAME, /* 0 */ | |
26 | GENERATION, /* 1 */ | |
27 | PCB_NAME, /* 2 */ | |
28 | FORM, /* 3 */ | |
29 | VERSION, /* 4 */ | |
30 | IDENTIFICATION_NUMBER, /* 5 */ | |
31 | MAJOR_SW_VERSION, /* 6 */ | |
32 | MINOR_SW_VERSION, /* 7 */ | |
33 | /* add new alements above this line */ | |
34 | HW_ID_ELEM_COUNT /* count */ | |
35 | }; | |
36 | ||
37 | /* | |
38 | * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition" | |
39 | */ | |
40 | ||
41 | #define DEVICE_NAME_OFFSET 0x02 | |
42 | #define GENERATION_OFFSET 0x0b | |
43 | #define PCB_NAME_OFFSET 0x0c | |
44 | #define FORM_OFFSET 0x15 | |
45 | #define VERSION_OFFSET 0x16 | |
46 | #define IDENTIFICATION_NUMBER_OFFSET 0x19 | |
47 | #define MAJOR_SW_VERSION_OFFSET 0x0480 | |
48 | #define MINOR_SW_VERSION_OFFSET 0x0481 | |
49 | ||
50 | ||
51 | #define DEVICE_NAME_LEN 0x09 | |
52 | #define GENERATION_LEN 0x01 | |
53 | #define PCB_NAME_LEN 0x09 | |
54 | #define FORM_LEN 0x01 | |
55 | #define VERSION_LEN 0x03 | |
56 | #define IDENTIFICATION_NUMBER_LEN 0x09 | |
57 | #define MAJOR_SW_VERSION_LEN 0x01 | |
58 | #define MINOR_SW_VERSION_LEN 0x01 | |
59 | ||
60 | #define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */ | |
61 | ||
62 | /* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */ | |
63 | #define MODULE_NAME_MAXLEN 64 | |
64 | ||
65 | ||
66 | /* storage for HW ID read from EEPROM */ | |
67 | typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN]; | |
68 | ||
69 | ||
70 | /* HW ID layout in EEPROM */ | |
71 | static struct { | |
72 | unsigned int offset; | |
73 | unsigned int length; | |
74 | } hw_id_format[HW_ID_ELEM_COUNT] = { | |
75 | {DEVICE_NAME_OFFSET, DEVICE_NAME_LEN}, | |
76 | {GENERATION_OFFSET, GENERATION_LEN}, | |
77 | {PCB_NAME_OFFSET, PCB_NAME_LEN}, | |
78 | {FORM_OFFSET, FORM_LEN}, | |
79 | {VERSION_OFFSET, VERSION_LEN}, | |
80 | {IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN}, | |
81 | {MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN}, | |
82 | {MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN}, | |
83 | }; | |
84 | ||
85 | ||
86 | /* HW ID data found in EEPROM on supported modules */ | |
87 | static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = { | |
88 | "CM", /* DEVICE_NAME */ | |
89 | "1", /* GENERATION */ | |
90 | "CM1", /* PCB_NAME */ | |
91 | "Q", /* FORM */ | |
92 | "A", /* VERSION */ | |
93 | "591881", /* IDENTIFICATION_NUMBER */ | |
94 | "", /* MAJOR_SW_VERSION */ | |
95 | "", /* MINOR_SW_VERSION */ | |
96 | }; | |
97 | ||
98 | static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = { | |
99 | "CM", /* DEVICE_NAME */ | |
100 | "1", /* GENERATION */ | |
101 | "CM11", /* PCB_NAME */ | |
102 | "Q", /* FORM */ | |
103 | "A", /* VERSION */ | |
104 | "594200", /* IDENTIFICATION_NUMBER */ | |
105 | "", /* MAJOR_SW_VERSION */ | |
106 | "", /* MINOR_SW_VERSION */ | |
107 | }; | |
108 | ||
109 | static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = { | |
110 | "CMU", /* DEVICE_NAME */ | |
111 | "1", /* GENERATION */ | |
112 | "CMU1", /* PCB_NAME */ | |
113 | "Q", /* FORM */ | |
114 | "A", /* VERSION */ | |
115 | "594128", /* IDENTIFICATION_NUMBER */ | |
116 | "", /* MAJOR_SW_VERSION */ | |
117 | "", /* MINOR_SW_VERSION */ | |
118 | }; | |
119 | ||
120 | ||
121 | /* list of known modules */ | |
122 | static char **hw_id_list[] = { | |
123 | cm1_qa_hw_id, | |
124 | cm11_qa_hw_id, | |
125 | cmu1_qa_hw_id, | |
126 | }; | |
127 | ||
be5d72d1 | 128 | /* indices to the above list - keep in sync */ |
86b116b1 BS |
129 | enum { |
130 | CM1_QA, | |
131 | CM11_QA, | |
132 | CMU1_QA, | |
133 | }; | |
134 | ||
135 | ||
136 | /* identify modules based on these hw id elements */ | |
137 | static int hw_id_identify[] = { | |
138 | PCB_NAME, | |
139 | FORM, | |
140 | VERSION, | |
141 | }; | |
142 | ||
143 | ||
144 | /* Registers' settings for SDRAM controller intialization */ | |
145 | typedef struct { | |
146 | ulong mode; | |
147 | ulong control; | |
148 | ulong config1; | |
149 | ulong config2; | |
150 | } mem_conf_t; | |
151 | ||
152 | static mem_conf_t k4s561632E = { | |
153 | 0x00CD0000, /* CASL 3, burst length 8 */ | |
154 | 0x514F0000, | |
155 | 0xE2333900, | |
156 | 0x8EE70000 | |
157 | }; | |
158 | ||
159 | static mem_conf_t mt48lc32m16a2 = { | |
160 | 0x00CD0000, /* CASL 3, burst length 8 */ | |
161 | 0x514F0000, | |
162 | 0xD2322800, | |
163 | 0x8AD70000 | |
164 | }; | |
165 | ||
166 | static mem_conf_t* memory_config[] = { | |
167 | &k4s561632E, | |
168 | &mt48lc32m16a2 | |
169 | }; | |
170 | ||
171 | #endif /* _CM5200_H */ |