[people/ms/u-boot.git] / board / cm_t35 / cm_t35.c

/*
 * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
 *
 * Authors: Mike Rapoport <mike@compulab.co.il>
 *	    Igor Grinberg <grinberg@compulab.co.il>
 *
 * Derived from omap3evm and Beagle Board by
 *	Manikandan Pillai <mani.pillai@ti.com>
 *	Richard Woodruff <r-woodruff2@ti.com>
 *	Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc.
 */

#include <common.h>
#include <status_led.h>
#include <netdev.h>
#include <net.h>
#include <i2c.h>
#include <twl4030.h>
#include <linux/compiler.h>

#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-types.h>

#include "eeprom.h"

DECLARE_GLOBAL_DATA_PTR;

const omap3_sysinfo sysinfo = {
	DDR_DISCRETE,
	"CM-T3x board",
	"NAND",
};

static u32 gpmc_net_config[GPMC_MAX_REG] = {
	NET_GPMC_CONFIG1,
	NET_GPMC_CONFIG2,
	NET_GPMC_CONFIG3,
	NET_GPMC_CONFIG4,
	NET_GPMC_CONFIG5,
	NET_GPMC_CONFIG6,
	0
};

static u32 gpmc_nand_config[GPMC_MAX_REG] = {
	SMNAND_GPMC_CONFIG1,
	SMNAND_GPMC_CONFIG2,
	SMNAND_GPMC_CONFIG3,
	SMNAND_GPMC_CONFIG4,
	SMNAND_GPMC_CONFIG5,
	SMNAND_GPMC_CONFIG6,
	0,
};

/*
 * Routine: board_init
 * Description: Early hardware init.
 */
int board_init(void)
{
	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */

	enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
			      CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);

	/* board id for Linux */
	if (get_cpu_family() == CPU_OMAP34XX)
		gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
	else
		gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;

	/* boot param addr */
	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);

#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
#endif

	return 0;
}

/*
 * Routine: misc_init_r
 * Description: display die ID
 */
int misc_init_r(void)
{
	dieid_num_r();

	return 0;
}

/*
 * Routine: set_muxconf_regs
 * Description: Setting up the configuration Mux registers specific to the
 *		hardware. Many pins need to be moved from protect to primary
 *		mode.
 */
static void cm_t3x_set_common_muxconf(void)
{
	/* SDRC */
	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)); /*SDRC_D0*/
	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)); /*SDRC_D1*/
	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)); /*SDRC_D2*/
	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)); /*SDRC_D3*/
	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)); /*SDRC_D4*/
	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)); /*SDRC_D5*/
	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)); /*SDRC_D6*/
	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)); /*SDRC_D7*/
	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)); /*SDRC_D8*/
	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)); /*SDRC_D9*/
	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)); /*SDRC_D10*/
	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)); /*SDRC_D11*/
	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)); /*SDRC_D12*/
	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)); /*SDRC_D13*/
	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)); /*SDRC_D14*/
	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)); /*SDRC_D15*/
	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)); /*SDRC_D16*/
	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)); /*SDRC_D17*/
	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)); /*SDRC_D18*/
	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)); /*SDRC_D19*/
	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)); /*SDRC_D20*/
	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)); /*SDRC_D21*/
	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)); /*SDRC_D22*/
	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)); /*SDRC_D23*/
	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)); /*SDRC_D24*/
	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)); /*SDRC_D25*/
	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)); /*SDRC_D26*/
	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)); /*SDRC_D27*/
	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)); /*SDRC_D28*/
	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)); /*SDRC_D29*/
	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)); /*SDRC_D30*/
	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)); /*SDRC_D31*/
	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)); /*SDRC_CLK*/
	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)); /*SDRC_DQS0*/
	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)); /*SDRC_DQS1*/
	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)); /*SDRC_DQS2*/
	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)); /*SDRC_DQS3*/
	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)); /*SDRC_CKE0*/
	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/

	/* GPMC */
	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)); /*GPMC_A1*/
	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)); /*GPMC_A2*/
	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)); /*GPMC_A3*/
	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)); /*GPMC_A4*/
	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)); /*GPMC_A5*/
	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)); /*GPMC_A6*/
	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)); /*GPMC_A7*/
	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)); /*GPMC_A8*/
	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)); /*GPMC_A9*/
	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)); /*GPMC_A10*/
	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)); /*GPMC_D0*/
	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)); /*GPMC_D1*/
	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)); /*GPMC_D2*/
	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)); /*GPMC_D3*/
	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)); /*GPMC_D4*/
	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)); /*GPMC_D5*/
	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)); /*GPMC_D6*/
	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)); /*GPMC_D7*/
	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)); /*GPMC_D8*/
	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)); /*GPMC_D9*/
	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)); /*GPMC_D10*/
	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)); /*GPMC_D11*/
	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)); /*GPMC_D12*/
	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)); /*GPMC_D13*/
	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)); /*GPMC_D14*/
	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)); /*GPMC_D15*/
	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)); /*GPMC_nCS0*/

	/* SB-T35 Ethernet */
	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)); /*GPMC_nCS4*/

	/* CM-T3x Ethernet */
	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
	MUX_VAL(CP(GPMC_CLK),		(IEN  | PTD | DIS | M4)); /*GPIO_59*/
	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)); /*nADV_ALE*/
	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)); /*nOE*/
	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)); /*nWE*/
	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)); /*nBE0_CLE*/
	MUX_VAL(CP(GPMC_NBE1),		(IDIS | PTD | DIS | M4)); /*GPIO_61*/
	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)); /*nWP*/
	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)); /*WAIT0*/

	/* DSS */
	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)); /*DSS_DATA17*/

	/* serial interface */
	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)); /*UART3_RX*/
	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)); /*UART3_TX*/

	/* mUSB */
	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)); /*HSUSB0_CLK*/
	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)); /*HSUSB0_STP*/
	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)); /*HSUSB0_DIR*/
	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)); /*HSUSB0_NXT*/
	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA0*/
	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA1*/
	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA2*/
	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA3*/
	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA4*/
	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA5*/
	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA6*/
	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)); /*HSUSB0_DATA7*/

	/* I2C1 */
	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)); /*I2C1_SCL*/
	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)); /*I2C1_SDA*/

	/* control and debug */
	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)); /*SYS_32K*/
	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)); /*SYS_CLKREQ*/
	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)); /*SYS_nIRQ*/
	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)); /*OFF_MODE*/
	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)); /*CLKOUT1*/
	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4)); /*green LED*/
	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)); /*JTAG_nTRST*/
	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)); /*JTAG_TCK*/
	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)); /*JTAG_TMS*/
	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)); /*JTAG_TDI*/

	/* MMC1 */
	MUX_VAL(CP(MMC1_CLK),		(IDIS | PTU | EN  | M0)); /*MMC1_CLK*/
	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | EN  | M0)); /*MMC1_CMD*/
	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | EN  | M0)); /*MMC1_DAT0*/
	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | EN  | M0)); /*MMC1_DAT1*/
	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | EN  | M0)); /*MMC1_DAT2*/
	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | EN  | M0)); /*MMC1_DAT3*/
}

static void cm_t35_set_muxconf(void)
{
	/* DSS */
	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)); /*DSS_DATA5*/

	MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
	MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
	MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
	MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
	MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
	MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/

	/* MMC1 */
	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M0)); /*MMC1_DAT4*/
	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M0)); /*MMC1_DAT5*/
	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M0)); /*MMC1_DAT6*/
	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M0)); /*MMC1_DAT7*/
}

static void cm_t3730_set_muxconf(void)
{
	/* DSS */
	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M3)); /*DSS_DATA5*/

	MUX_VAL(CP(SYS_BOOT0),		(IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
	MUX_VAL(CP(SYS_BOOT1),		(IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
	MUX_VAL(CP(SYS_BOOT3),		(IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
	MUX_VAL(CP(SYS_BOOT4),		(IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
	MUX_VAL(CP(SYS_BOOT5),		(IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
}

void set_muxconf_regs(void)
{
	cm_t3x_set_common_muxconf();

	if (get_cpu_family() == CPU_OMAP34XX)
		cm_t35_set_muxconf();
	else
		cm_t3730_set_muxconf();
}

#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
	return omap_mmc_init(0, 0, 0);
}
#endif

/*
 * Routine: setup_net_chip_gmpc
 * Description: Setting up the configuration GPMC registers specific to the
 *		Ethernet hardware.
 */
static void setup_net_chip_gmpc(void)
{
	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;

	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
			      CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
			      SB_T35_SMC911X_BASE, GPMC_SIZE_16M);

	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);

	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);

	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
		&ctrl_base->gpmc_nadv_ale);
}

#ifdef CONFIG_DRIVER_OMAP34XX_I2C
/*
 * Routine: reset_net_chip
 * Description: reset the Ethernet controller via TPS65930 GPIO
 */
static void reset_net_chip(void)
{
	/* Set GPIO1 of TPS65930 as output */
	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
				TWL4030_BASEADD_GPIO + 0x03);
	/* Send a pulse on the GPIO pin */
	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
				TWL4030_BASEADD_GPIO + 0x0C);
	udelay(1);
	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
				TWL4030_BASEADD_GPIO + 0x09);
	mdelay(40);
	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
				TWL4030_BASEADD_GPIO + 0x0C);
	mdelay(1);
}
#else
static inline void reset_net_chip(void) {}
#endif

#ifdef CONFIG_SMC911X
/*
 * Routine: handle_mac_address
 * Description: prepare MAC address for on-board Ethernet.
 */
static int handle_mac_address(void)
{
	unsigned char enetaddr[6];
	int rc;

	rc = eth_getenv_enetaddr("ethaddr", enetaddr);
	if (rc)
		return 0;

	rc = cm_t3x_eeprom_read_mac_addr(enetaddr);
	if (rc)
		return rc;

	if (!is_valid_ether_addr(enetaddr))
		return -1;

	return eth_setenv_enetaddr("ethaddr", enetaddr);
}


/*
 * Routine: board_eth_init
 * Description: initialize module and base-board Ethernet chips
 */
int board_eth_init(bd_t *bis)
{
	int rc = 0, rc1 = 0;

	setup_net_chip_gmpc();
	reset_net_chip();

	rc1 = handle_mac_address();
	if (rc1)
		printf("CM-T3x: No MAC address found\n");

	rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
	if (rc1 > 0)
		rc++;

	rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
	if (rc1 > 0)
		rc++;

	return rc;
}
#endif

void __weak get_board_serial(struct tag_serialnr *serialnr)
{
	/*
	 * This corresponds to what happens when we can communicate with the
	 * eeprom but don't get a valid board serial value.
	 */
	serialnr->low = 0;
	serialnr->high = 0;
};
Commit	Line	Data
36b4e2dd	1	/*
ce15ec9f	2	* (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
36b4e2dd	3	*
dccd9a0b IG	4	* Authors: Mike Rapoport <mike@compulab.co.il>
dccd9a0b IG	5	* Igor Grinberg <grinberg@compulab.co.il>
36b4e2dd MR	6	*
	7	* Derived from omap3evm and Beagle Board by
	8	* Manikandan Pillai <mani.pillai@ti.com>
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <x0khasim@ti.com>
	11	*
	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
dccd9a0b	27	* Foundation, Inc.
36b4e2dd MR	28	*/
	29
	30	#include <common.h>
2b8754b2	31	#include <status_led.h>
36b4e2dd MR	32	#include <netdev.h>
	33	#include <net.h>
	34	#include <i2c.h>
	35	#include <twl4030.h>
82309250	36	#include <linux/compiler.h>
36b4e2dd MR	37
	38	#include <asm/io.h>
	39	#include <asm/arch/mem.h>
	40	#include <asm/arch/mux.h>
	41	#include <asm/arch/mmc_host_def.h>
	42	#include <asm/arch/sys_proto.h>
	43	#include <asm/mach-types.h>
	44
e4e2bf5e NK	45	#include "eeprom.h"
e4e2bf5e NK	46
557aa155 IG	47	DECLARE_GLOBAL_DATA_PTR;
557aa155 IG	48
36b4e2dd MR	49	const omap3_sysinfo sysinfo = {
36b4e2dd MR	50	DDR_DISCRETE,
b65a77a8	51	"CM-T3x board",
36b4e2dd MR	52	"NAND",
	53	};
	54
	55	static u32 gpmc_net_config[GPMC_MAX_REG] = {
	56	NET_GPMC_CONFIG1,
	57	NET_GPMC_CONFIG2,
	58	NET_GPMC_CONFIG3,
	59	NET_GPMC_CONFIG4,
	60	NET_GPMC_CONFIG5,
	61	NET_GPMC_CONFIG6,
	62	0
	63	};
	64
	65	static u32 gpmc_nand_config[GPMC_MAX_REG] = {
	66	SMNAND_GPMC_CONFIG1,
	67	SMNAND_GPMC_CONFIG2,
	68	SMNAND_GPMC_CONFIG3,
	69	SMNAND_GPMC_CONFIG4,
	70	SMNAND_GPMC_CONFIG5,
	71	SMNAND_GPMC_CONFIG6,
	72	0,
	73	};
	74
	75	/*
	76	* Routine: board_init
	77	* Description: Early hardware init.
	78	*/
	79	int board_init(void)
	80	{
36b4e2dd MR	81	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
	82
	83	enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
	84	CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
	85
	86	/* board id for Linux */
b65a77a8 IG	87	if (get_cpu_family() == CPU_OMAP34XX)
	88	gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
	89	else
	90	gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
	91
36b4e2dd MR	92	/* boot param addr */
	93	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
	94
2b8754b2 IG	95	#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
	96	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
	97	#endif
	98
36b4e2dd MR	99	return 0;
	100	}
	101
	102	/*
	103	* Routine: misc_init_r
afff1fc0	104	* Description: display die ID
36b4e2dd MR	105	*/
	106	int misc_init_r(void)
	107	{
36b4e2dd MR	108	dieid_num_r();
	109
	110	return 0;
	111	}
	112
	113	/*
	114	* Routine: set_muxconf_regs
	115	* Description: Setting up the configuration Mux registers specific to the
	116	* hardware. Many pins need to be moved from protect to primary
	117	* mode.
	118	*/
b65a77a8	119	static void cm_t3x_set_common_muxconf(void)
36b4e2dd MR	120	{
	121	/* SDRC */
	122	MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)); /SDRC_D0/
	123	MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)); /SDRC_D1/
	124	MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)); /SDRC_D2/
	125	MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)); /SDRC_D3/
	126	MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)); /SDRC_D4/
	127	MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)); /SDRC_D5/
	128	MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)); /SDRC_D6/
	129	MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)); /SDRC_D7/
	130	MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)); /SDRC_D8/
	131	MUX_VAL(CP(SDRC_D9), (IEN \| PTD \| DIS \| M0)); /SDRC_D9/
	132	MUX_VAL(CP(SDRC_D10), (IEN \| PTD \| DIS \| M0)); /SDRC_D10/
	133	MUX_VAL(CP(SDRC_D11), (IEN \| PTD \| DIS \| M0)); /SDRC_D11/
	134	MUX_VAL(CP(SDRC_D12), (IEN \| PTD \| DIS \| M0)); /SDRC_D12/
	135	MUX_VAL(CP(SDRC_D13), (IEN \| PTD \| DIS \| M0)); /SDRC_D13/
	136	MUX_VAL(CP(SDRC_D14), (IEN \| PTD \| DIS \| M0)); /SDRC_D14/
	137	MUX_VAL(CP(SDRC_D15), (IEN \| PTD \| DIS \| M0)); /SDRC_D15/
	138	MUX_VAL(CP(SDRC_D16), (IEN \| PTD \| DIS \| M0)); /SDRC_D16/
	139	MUX_VAL(CP(SDRC_D17), (IEN \| PTD \| DIS \| M0)); /SDRC_D17/
	140	MUX_VAL(CP(SDRC_D18), (IEN \| PTD \| DIS \| M0)); /SDRC_D18/
	141	MUX_VAL(CP(SDRC_D19), (IEN \| PTD \| DIS \| M0)); /SDRC_D19/
	142	MUX_VAL(CP(SDRC_D20), (IEN \| PTD \| DIS \| M0)); /SDRC_D20/
	143	MUX_VAL(CP(SDRC_D21), (IEN \| PTD \| DIS \| M0)); /SDRC_D21/
	144	MUX_VAL(CP(SDRC_D22), (IEN \| PTD \| DIS \| M0)); /SDRC_D22/
	145	MUX_VAL(CP(SDRC_D23), (IEN \| PTD \| DIS \| M0)); /SDRC_D23/
	146	MUX_VAL(CP(SDRC_D24), (IEN \| PTD \| DIS \| M0)); /SDRC_D24/
	147	MUX_VAL(CP(SDRC_D25), (IEN \| PTD \| DIS \| M0)); /SDRC_D25/
	148	MUX_VAL(CP(SDRC_D26), (IEN \| PTD \| DIS \| M0)); /SDRC_D26/
	149	MUX_VAL(CP(SDRC_D27), (IEN \| PTD \| DIS \| M0)); /SDRC_D27/
	150	MUX_VAL(CP(SDRC_D28), (IEN \| PTD \| DIS \| M0)); /SDRC_D28/
	151	MUX_VAL(CP(SDRC_D29), (IEN \| PTD \| DIS \| M0)); /SDRC_D29/
	152	MUX_VAL(CP(SDRC_D30), (IEN \| PTD \| DIS \| M0)); /SDRC_D30/
	153	MUX_VAL(CP(SDRC_D31), (IEN \| PTD \| DIS \| M0)); /SDRC_D31/
	154	MUX_VAL(CP(SDRC_CLK), (IEN \| PTD \| DIS \| M0)); /SDRC_CLK/
	155	MUX_VAL(CP(SDRC_DQS0), (IEN \| PTD \| DIS \| M0)); /SDRC_DQS0/
	156	MUX_VAL(CP(SDRC_DQS1), (IEN \| PTD \| DIS \| M0)); /SDRC_DQS1/
	157	MUX_VAL(CP(SDRC_DQS2), (IEN \| PTD \| DIS \| M0)); /SDRC_DQS2/
	158	MUX_VAL(CP(SDRC_DQS3), (IEN \| PTD \| DIS \| M0)); /SDRC_DQS3/
	159	MUX_VAL(CP(SDRC_CKE0), (IDIS \| PTU \| EN \| M0)); /SDRC_CKE0/
	160	MUX_VAL(CP(SDRC_CKE1), (IDIS \| PTD \| DIS \| M7)); /SDRC_CKE1/
	161
	162	/* GPMC */
	163	MUX_VAL(CP(GPMC_A1), (IDIS \| PTU \| EN \| M0)); /GPMC_A1/
	164	MUX_VAL(CP(GPMC_A2), (IDIS \| PTU \| EN \| M0)); /GPMC_A2/
	165	MUX_VAL(CP(GPMC_A3), (IDIS \| PTU \| EN \| M0)); /GPMC_A3/
	166	MUX_VAL(CP(GPMC_A4), (IDIS \| PTU \| EN \| M0)); /GPMC_A4/
	167	MUX_VAL(CP(GPMC_A5), (IDIS \| PTU \| EN \| M0)); /GPMC_A5/
	168	MUX_VAL(CP(GPMC_A6), (IDIS \| PTU \| EN \| M0)); /GPMC_A6/
	169	MUX_VAL(CP(GPMC_A7), (IDIS \| PTU \| EN \| M0)); /GPMC_A7/
	170	MUX_VAL(CP(GPMC_A8), (IDIS \| PTU \| EN \| M0)); /GPMC_A8/
	171	MUX_VAL(CP(GPMC_A9), (IDIS \| PTU \| EN \| M0)); /GPMC_A9/
	172	MUX_VAL(CP(GPMC_A10), (IDIS \| PTU \| EN \| M0)); /GPMC_A10/
	173	MUX_VAL(CP(GPMC_D0), (IEN \| PTU \| EN \| M0)); /GPMC_D0/
	174	MUX_VAL(CP(GPMC_D1), (IEN \| PTU \| EN \| M0)); /GPMC_D1/
	175	MUX_VAL(CP(GPMC_D2), (IEN \| PTU \| EN \| M0)); /GPMC_D2/
	176	MUX_VAL(CP(GPMC_D3), (IEN \| PTU \| EN \| M0)); /GPMC_D3/
	177	MUX_VAL(CP(GPMC_D4), (IEN \| PTU \| EN \| M0)); /GPMC_D4/
	178	MUX_VAL(CP(GPMC_D5), (IEN \| PTU \| EN \| M0)); /GPMC_D5/
	179	MUX_VAL(CP(GPMC_D6), (IEN \| PTU \| EN \| M0)); /GPMC_D6/
	180	MUX_VAL(CP(GPMC_D7), (IEN \| PTU \| EN \| M0)); /GPMC_D7/
	181	MUX_VAL(CP(GPMC_D8), (IEN \| PTU \| EN \| M0)); /GPMC_D8/
	182	MUX_VAL(CP(GPMC_D9), (IEN \| PTU \| EN \| M0)); /GPMC_D9/
	183	MUX_VAL(CP(GPMC_D10), (IEN \| PTU \| EN \| M0)); /GPMC_D10/
184	MUX_VAL(CP(GPMC_D11), (IEN \| PTU \| EN \| M0)); /GPMC_D11/
185	MUX_VAL(CP(GPMC_D12), (IEN \| PTU \| EN \| M0)); /GPMC_D12/
186	MUX_VAL(CP(GPMC_D13), (IEN \| PTU \| EN \| M0)); /GPMC_D13/
187	MUX_VAL(CP(GPMC_D14), (IEN \| PTU \| EN \| M0)); /GPMC_D14/
188	MUX_VAL(CP(GPMC_D15), (IEN \| PTU \| EN \| M0)); /GPMC_D15/
189	MUX_VAL(CP(GPMC_NCS0), (IDIS \| PTU \| EN \| M0)); /GPMC_nCS0/
190
191	/* SB-T35 Ethernet */
192	MUX_VAL(CP(GPMC_NCS4), (IEN \| PTU \| EN \| M0)); /GPMC_nCS4/
193
b65a77a8	194	/* CM-T3x Ethernet */
36b4e2dd MR	195	MUX_VAL(CP(GPMC_NCS5), (IDIS \| PTU \| DIS \| M0)); /GPMC_nCS5/
	196	MUX_VAL(CP(GPMC_CLK), (IEN \| PTD \| DIS \| M4)); /GPIO_59/
	197	MUX_VAL(CP(GPMC_NADV_ALE), (IDIS \| PTD \| DIS \| M0)); /nADV_ALE/
	198	MUX_VAL(CP(GPMC_NOE), (IDIS \| PTD \| DIS \| M0)); /nOE/
	199	MUX_VAL(CP(GPMC_NWE), (IDIS \| PTD \| DIS \| M0)); /nWE/
	200	MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS \| PTU \| EN \| M0)); /nBE0_CLE/
	201	MUX_VAL(CP(GPMC_NBE1), (IDIS \| PTD \| DIS \| M4)); /GPIO_61/
	202	MUX_VAL(CP(GPMC_NWP), (IEN \| PTD \| DIS \| M0)); /nWP/
	203	MUX_VAL(CP(GPMC_WAIT0), (IEN \| PTU \| EN \| M0)); /WAIT0/
	204
	205	/* DSS */
	206	MUX_VAL(CP(DSS_PCLK), (IDIS \| PTD \| DIS \| M0)); /DSS_PCLK/
	207	MUX_VAL(CP(DSS_HSYNC), (IDIS \| PTD \| DIS \| M0)); /DSS_HSYNC/
	208	MUX_VAL(CP(DSS_VSYNC), (IDIS \| PTD \| DIS \| M0)); /DSS_VSYNC/
	209	MUX_VAL(CP(DSS_ACBIAS), (IDIS \| PTD \| DIS \| M0)); /DSS_ACBIAS/
36b4e2dd MR	210	MUX_VAL(CP(DSS_DATA6), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA6/
	211	MUX_VAL(CP(DSS_DATA7), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA7/
	212	MUX_VAL(CP(DSS_DATA8), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA8/
	213	MUX_VAL(CP(DSS_DATA9), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA9/
	214	MUX_VAL(CP(DSS_DATA10), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA10/
	215	MUX_VAL(CP(DSS_DATA11), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA11/
	216	MUX_VAL(CP(DSS_DATA12), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA12/
	217	MUX_VAL(CP(DSS_DATA13), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA13/
	218	MUX_VAL(CP(DSS_DATA14), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA14/
	219	MUX_VAL(CP(DSS_DATA15), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA15/
	220	MUX_VAL(CP(DSS_DATA16), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA16/
	221	MUX_VAL(CP(DSS_DATA17), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA17/
36b4e2dd MR	222
	223	/* serial interface */
	224	MUX_VAL(CP(UART3_RX_IRRX), (IEN \| PTD \| DIS \| M0)); /UART3_RX/
	225	MUX_VAL(CP(UART3_TX_IRTX), (IDIS \| PTD \| DIS \| M0)); /UART3_TX/
	226
	227	/* mUSB */
	228	MUX_VAL(CP(HSUSB0_CLK), (IEN \| PTD \| DIS \| M0)); /HSUSB0_CLK/
	229	MUX_VAL(CP(HSUSB0_STP), (IDIS \| PTU \| EN \| M0)); /HSUSB0_STP/
	230	MUX_VAL(CP(HSUSB0_DIR), (IEN \| PTD \| DIS \| M0)); /HSUSB0_DIR/
	231	MUX_VAL(CP(HSUSB0_NXT), (IEN \| PTD \| DIS \| M0)); /HSUSB0_NXT/
	232	MUX_VAL(CP(HSUSB0_DATA0), (IEN \| PTD \| DIS \| M0)); /HSUSB0_DATA0/
	233	MUX_VAL(CP(HSUSB0_DATA1), (IEN \| PTD \| DIS \| M0)); /HSUSB0_DATA1/
	234	MUX_VAL(CP(HSUSB0_DATA2), (IEN \| PTD \| DIS \| M0)); /HSUSB0_DATA2/
	235	MUX_VAL(CP(HSUSB0_DATA3), (IEN \| PTD \| DIS \| M0)); /HSUSB0_DATA3/
	236	MUX_VAL(CP(HSUSB0_DATA4), (IEN \| PTD \| DIS \| M0)); /HSUSB0_DATA4/
	237	MUX_VAL(CP(HSUSB0_DATA5), (IEN \| PTD \| DIS \| M0)); /HSUSB0_DATA5/
	238	MUX_VAL(CP(HSUSB0_DATA6), (IEN \| PTD \| DIS \| M0)); /HSUSB0_DATA6/
	239	MUX_VAL(CP(HSUSB0_DATA7), (IEN \| PTD \| DIS \| M0)); /HSUSB0_DATA7/
	240
	241	/* I2C1 */
	242	MUX_VAL(CP(I2C1_SCL), (IEN \| PTU \| EN \| M0)); /I2C1_SCL/
	243	MUX_VAL(CP(I2C1_SDA), (IEN \| PTU \| EN \| M0)); /I2C1_SDA/
	244
	245	/* control and debug */
	246	MUX_VAL(CP(SYS_32K), (IEN \| PTD \| DIS \| M0)); /SYS_32K/
	247	MUX_VAL(CP(SYS_CLKREQ), (IEN \| PTD \| DIS \| M0)); /SYS_CLKREQ/
	248	MUX_VAL(CP(SYS_NIRQ), (IEN \| PTU \| EN \| M0)); /SYS_nIRQ/
	249	MUX_VAL(CP(SYS_OFF_MODE), (IEN \| PTD \| DIS \| M0)); /OFF_MODE/
	250	MUX_VAL(CP(SYS_CLKOUT1), (IEN \| PTD \| DIS \| M0)); /CLKOUT1/
2b8754b2	251	MUX_VAL(CP(SYS_CLKOUT2), (IDIS \| PTU \| DIS \| M4)); /green LED/
36b4e2dd MR	252	MUX_VAL(CP(JTAG_nTRST), (IEN \| PTD \| DIS \| M0)); /JTAG_nTRST/
	253	MUX_VAL(CP(JTAG_TCK), (IEN \| PTD \| DIS \| M0)); /JTAG_TCK/
	254	MUX_VAL(CP(JTAG_TMS), (IEN \| PTD \| DIS \| M0)); /JTAG_TMS/
	255	MUX_VAL(CP(JTAG_TDI), (IEN \| PTD \| DIS \| M0)); /JTAG_TDI/
eec70c2d IG	256
	257	/* MMC1 */
	258	MUX_VAL(CP(MMC1_CLK), (IDIS \| PTU \| EN \| M0)); /MMC1_CLK/
	259	MUX_VAL(CP(MMC1_CMD), (IEN \| PTU \| EN \| M0)); /MMC1_CMD/
	260	MUX_VAL(CP(MMC1_DAT0), (IEN \| PTU \| EN \| M0)); /MMC1_DAT0/
	261	MUX_VAL(CP(MMC1_DAT1), (IEN \| PTU \| EN \| M0)); /MMC1_DAT1/
	262	MUX_VAL(CP(MMC1_DAT2), (IEN \| PTU \| EN \| M0)); /MMC1_DAT2/
	263	MUX_VAL(CP(MMC1_DAT3), (IEN \| PTU \| EN \| M0)); /MMC1_DAT3/
b65a77a8 IG	264	}
	265
	266	static void cm_t35_set_muxconf(void)
	267	{
	268	/* DSS */
	269	MUX_VAL(CP(DSS_DATA0), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA0/
	270	MUX_VAL(CP(DSS_DATA1), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA1/
	271	MUX_VAL(CP(DSS_DATA2), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA2/
	272	MUX_VAL(CP(DSS_DATA3), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA3/
	273	MUX_VAL(CP(DSS_DATA4), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA4/
	274	MUX_VAL(CP(DSS_DATA5), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA5/
	275
	276	MUX_VAL(CP(DSS_DATA18), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA18/
	277	MUX_VAL(CP(DSS_DATA19), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA19/
	278	MUX_VAL(CP(DSS_DATA20), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA20/
	279	MUX_VAL(CP(DSS_DATA21), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA21/
	280	MUX_VAL(CP(DSS_DATA22), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA22/
	281	MUX_VAL(CP(DSS_DATA23), (IDIS \| PTD \| DIS \| M0)); /DSS_DATA23/
	282
	283	/* MMC1 */
eec70c2d IG	284	MUX_VAL(CP(MMC1_DAT4), (IEN \| PTU \| EN \| M0)); /MMC1_DAT4/
	285	MUX_VAL(CP(MMC1_DAT5), (IEN \| PTU \| EN \| M0)); /MMC1_DAT5/
	286	MUX_VAL(CP(MMC1_DAT6), (IEN \| PTU \| EN \| M0)); /MMC1_DAT6/
	287	MUX_VAL(CP(MMC1_DAT7), (IEN \| PTU \| EN \| M0)); /MMC1_DAT7/
36b4e2dd MR	288	}
36b4e2dd MR	289
b65a77a8 IG	290	static void cm_t3730_set_muxconf(void)
	291	{
	292	/* DSS */
	293	MUX_VAL(CP(DSS_DATA18), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA0/
	294	MUX_VAL(CP(DSS_DATA19), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA1/
	295	MUX_VAL(CP(DSS_DATA20), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA2/
	296	MUX_VAL(CP(DSS_DATA21), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA3/
	297	MUX_VAL(CP(DSS_DATA22), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA4/
	298	MUX_VAL(CP(DSS_DATA23), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA5/
	299
	300	MUX_VAL(CP(SYS_BOOT0), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA18/
	301	MUX_VAL(CP(SYS_BOOT1), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA19/
	302	MUX_VAL(CP(SYS_BOOT3), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA20/
	303	MUX_VAL(CP(SYS_BOOT4), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA21/
	304	MUX_VAL(CP(SYS_BOOT5), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA22/
	305	MUX_VAL(CP(SYS_BOOT6), (IDIS \| PTD \| DIS \| M3)); /DSS_DATA23/
	306	}
	307
	308	void set_muxconf_regs(void)
	309	{
	310	cm_t3x_set_common_muxconf();
	311
	312	if (get_cpu_family() == CPU_OMAP34XX)
	313	cm_t35_set_muxconf();
	314	else
	315	cm_t3730_set_muxconf();
	316	}
	317
28fed362 TR	318	#ifdef CONFIG_GENERIC_MMC
	319	int board_mmc_init(bd_t *bis)
	320	{
bbbc1ae9	321	return omap_mmc_init(0, 0, 0);
28fed362 TR	322	}
	323	#endif
	324
36b4e2dd MR	325	/*
	326	* Routine: setup_net_chip_gmpc
	327	* Description: Setting up the configuration GPMC registers specific to the
	328	* Ethernet hardware.
	329	*/
	330	static void setup_net_chip_gmpc(void)
	331	{
	332	struct ctrl ctrl_base = (struct ctrl )OMAP34XX_CTRL_BASE;
	333
	334	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
b65a77a8	335	CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
36b4e2dd MR	336	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
	337	SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
	338
	339	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
	340	writew(readw(&ctrl_base->gpmc_nwe) \| 0x0E00, &ctrl_base->gpmc_nwe);
	341
	342	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
	343	writew(readw(&ctrl_base->gpmc_noe) \| 0x0E00, &ctrl_base->gpmc_noe);
	344
	345	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
	346	writew(readw(&ctrl_base->gpmc_nadv_ale) \| 0x0E00,
	347	&ctrl_base->gpmc_nadv_ale);
	348	}
	349
	350	#ifdef CONFIG_DRIVER_OMAP34XX_I2C
	351	/*
	352	* Routine: reset_net_chip
	353	* Description: reset the Ethernet controller via TPS65930 GPIO
	354	*/
	355	static void reset_net_chip(void)
	356	{
	357	/* Set GPIO1 of TPS65930 as output */
	358	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
07277e74	359	TWL4030_BASEADD_GPIO + 0x03);
36b4e2dd MR	360	/* Send a pulse on the GPIO pin */
36b4e2dd MR	361	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
07277e74	362	TWL4030_BASEADD_GPIO + 0x0C);
36b4e2dd MR	363	udelay(1);
36b4e2dd MR	364	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
07277e74 IG	365	TWL4030_BASEADD_GPIO + 0x09);
07277e74 IG	366	mdelay(40);
36b4e2dd	367	twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
07277e74 IG	368	TWL4030_BASEADD_GPIO + 0x0C);
07277e74 IG	369	mdelay(1);
36b4e2dd MR	370	}
	371	#else
	372	static inline void reset_net_chip(void) {}
	373	#endif
	374
ce15ec9f	375	#ifdef CONFIG_SMC911X
36b4e2dd MR	376	/*
	377	* Routine: handle_mac_address
	378	* Description: prepare MAC address for on-board Ethernet.
	379	*/
	380	static int handle_mac_address(void)
	381	{
	382	unsigned char enetaddr[6];
	383	int rc;
	384
	385	rc = eth_getenv_enetaddr("ethaddr", enetaddr);
	386	if (rc)
	387	return 0;
	388
e4e2bf5e	389	rc = cm_t3x_eeprom_read_mac_addr(enetaddr);
36b4e2dd MR	390	if (rc)
36b4e2dd MR	391	return rc;
36b4e2dd MR	392
	393	if (!is_valid_ether_addr(enetaddr))
	394	return -1;
	395
	396	return eth_setenv_enetaddr("ethaddr", enetaddr);
	397	}
	398
	399
	400	/*
	401	* Routine: board_eth_init
	402	* Description: initialize module and base-board Ethernet chips
	403	*/
	404	int board_eth_init(bd_t *bis)
	405	{
	406	int rc = 0, rc1 = 0;
	407
36b4e2dd MR	408	setup_net_chip_gmpc();
	409	reset_net_chip();
	410
	411	rc1 = handle_mac_address();
	412	if (rc1)
b65a77a8	413	printf("CM-T3x: No MAC address found\n");
36b4e2dd	414
b65a77a8	415	rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
36b4e2dd MR	416	if (rc1 > 0)
	417	rc++;
	418
	419	rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
	420	if (rc1 > 0)
	421	rc++;
36b4e2dd MR	422
	423	return rc;
	424	}
ce15ec9f	425	#endif
82309250 NK	426
	427	void __weak get_board_serial(struct tag_serialnr *serialnr)
	428	{
	429	/*
	430	* This corresponds to what happens when we can communicate with the
	431	* eeprom but don't get a valid board serial value.
	432	*/
	433	serialnr->low = 0;
	434	serialnr->high = 0;
	435	};