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2996e2dc SW |
1 | /* |
2 | * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | */ | |
16 | ||
17 | #include <common.h> | |
18 | #include <asm/io.h> | |
150c2493 | 19 | #include <asm/arch/tegra.h> |
2996e2dc | 20 | #include <asm/arch/pinmux.h> |
150c2493 | 21 | #include <asm/arch-tegra/mmc.h> |
2996e2dc | 22 | #include <asm/gpio.h> |
1e2d7859 | 23 | #ifdef CONFIG_TEGRA_MMC |
2996e2dc SW |
24 | #include <mmc.h> |
25 | #endif | |
26 | ||
2996e2dc | 27 | |
1e2d7859 | 28 | #ifdef CONFIG_TEGRA_MMC |
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29 | /* |
30 | * Routine: pin_mux_mmc | |
31 | * Description: setup the pin muxes/tristate values for the SDMMC(s) | |
32 | */ | |
33 | static void pin_mux_mmc(void) | |
34 | { | |
35 | /* SDMMC4: config 3, x8 on 2nd set of pins */ | |
36 | pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4); | |
37 | pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4); | |
38 | pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4); | |
39 | ||
40 | pinmux_tristate_disable(PINGRP_ATB); | |
41 | pinmux_tristate_disable(PINGRP_GMA); | |
42 | pinmux_tristate_disable(PINGRP_GME); | |
43 | ||
ffec1eb9 LS |
44 | /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ |
45 | pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1); | |
2996e2dc | 46 | |
ffec1eb9 | 47 | pinmux_tristate_disable(PINGRP_SDIO1); |
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48 | |
49 | /* For power GPIO PV1 */ | |
50 | pinmux_tristate_disable(PINGRP_UAC); | |
aa53c7f5 SW |
51 | /* For CD GPIO PV5 */ |
52 | pinmux_tristate_disable(PINGRP_GPV); | |
2996e2dc SW |
53 | } |
54 | ||
55 | /* this is a weak define that we are overriding */ | |
56 | int board_mmc_init(bd_t *bd) | |
57 | { | |
58 | debug("board_mmc_init called\n"); | |
59 | ||
60 | /* Enable muxes, etc. for SDMMC controllers */ | |
61 | pin_mux_mmc(); | |
62 | ||
63 | debug("board_mmc_init: init eMMC\n"); | |
72573543 SW |
64 | /* init dev 0, eMMC chip, with 8-bit bus */ |
65 | tegra_mmc_init(0, 8, -1, -1); | |
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66 | |
67 | debug("board_mmc_init: init SD slot\n"); | |
68 | /* init dev 3, SD slot, with 4-bit bus */ | |
29f3e3f2 | 69 | tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); |
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70 | |
71 | return 0; | |
72 | } | |
73 | #endif | |
25dccd6f MD |
74 | |
75 | #ifdef CONFIG_LCD | |
76 | /* this is a weak define that we are overriding */ | |
77 | void pin_mux_display(void) | |
78 | { | |
79 | debug("init display pinmux\n"); | |
80 | ||
81 | /* EN_VDD_PANEL GPIO A4 */ | |
82 | pinmux_tristate_disable(PINGRP_DAP2); | |
83 | } | |
84 | #endif |