projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 2996e2dc SW |
1 | /* |
| 2 | * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. | |
| 3 | * | |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify it | |
| 8 | * under the terms and conditions of the GNU General Public License, | |
| 9 | * version 2, as published by the Free Software Foundation. | |
| 10 | * | |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 14 | * more details. | |
| 15 | */ | |
| 16 | ||
| 17 | #include <common.h> | |
| 18 | #include <asm/io.h> | |
| 19 | #include <asm/arch/tegra2.h> | |
| 20 | #include <asm/arch/pinmux.h> | |
| 21 | #include <asm/arch/mmc.h> | |
| 22 | #include <asm/gpio.h> | |
| 23 | #ifdef CONFIG_TEGRA2_MMC | |
| 24 | #include <mmc.h> | |
| 25 | #endif | |
| 26 | ||
| 27 | /* | |
| 28 | * Routine: gpio_config_uart | |
| 29 | * Description: Does nothing on Paz00 - no conflict w/SPI. | |
| 30 | */ | |
| 31 | void gpio_config_uart(void) | |
| 32 | { | |
| 33 | } | |
| 34 | ||
| 35 | #ifdef CONFIG_TEGRA2_MMC | |
| 36 | /* | |
| 37 | * Routine: pin_mux_mmc | |
| 38 | * Description: setup the pin muxes/tristate values for the SDMMC(s) | |
| 39 | */ | |
| 40 | static void pin_mux_mmc(void) | |
| 41 | { | |
| 42 | /* SDMMC4: config 3, x8 on 2nd set of pins */ | |
| 43 | pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4); | |
| 44 | pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4); | |
| 45 | pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4); | |
| 46 | ||
| 47 | pinmux_tristate_disable(PINGRP_ATB); | |
| 48 | pinmux_tristate_disable(PINGRP_GMA); | |
| 49 | pinmux_tristate_disable(PINGRP_GME); | |
| 50 | ||
| 51 | /* SDMMC1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ | |
| 52 | pinmux_set_func(PINGRP_SDMMC1, PMUX_FUNC_SDIO1); | |
| 53 | ||
| 54 | pinmux_tristate_disable(PINGRP_SDMMC1); | |
| 55 | ||
| 56 | /* For power GPIO PV1 */ | |
| 57 | pinmux_tristate_disable(PINGRP_UAC); | |
| aa53c7f5 SW |
58 | /* For CD GPIO PV5 */ |
| 59 | pinmux_tristate_disable(PINGRP_GPV); | |
| 2996e2dc SW |
60 | } |
| 61 | ||
| 62 | /* this is a weak define that we are overriding */ | |
| 63 | int board_mmc_init(bd_t *bd) | |
| 64 | { | |
| 65 | debug("board_mmc_init called\n"); | |
| 66 | ||
| 67 | /* Enable muxes, etc. for SDMMC controllers */ | |
| 68 | pin_mux_mmc(); | |
| 69 | ||
| 70 | debug("board_mmc_init: init eMMC\n"); | |
| 71 | /* init dev 0, eMMC chip, with 4-bit bus */ | |
| 72 | /* The board has an 8-bit bus, but 8-bit doesn't work yet */ | |
| 73 | tegra2_mmc_init(0, 4, -1, -1); | |
| 74 | ||
| 75 | debug("board_mmc_init: init SD slot\n"); | |
| 76 | /* init dev 3, SD slot, with 4-bit bus */ | |
| aa53c7f5 | 77 | tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); |
| 2996e2dc SW |
78 | |
| 79 | return 0; | |
| 80 | } | |
| 81 | #endif |