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fc300e2c DL |
1 | /* |
2 | * Ethernet specific code for CompuLab CL-SOM-AM57x module | |
3 | * | |
4 | * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/ | |
5 | * | |
6 | * Author: Uri Mashiach <uri.mashiach@compulab.co.il> | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
11 | #include <common.h> | |
12 | #include <cpsw.h> | |
13 | #include <miiphy.h> | |
14 | #include <asm/gpio.h> | |
15 | #include <asm/arch/sys_proto.h> | |
16 | #include "../common/eeprom.h" | |
17 | ||
18 | static void cpsw_control(int enabled) | |
19 | { | |
20 | /* VTP can be added here */ | |
21 | } | |
22 | ||
23 | static struct cpsw_slave_data cl_som_am57x_cpsw_slaves[] = { | |
24 | { | |
25 | .slave_reg_ofs = 0x208, | |
26 | .sliver_reg_ofs = 0xd80, | |
27 | .phy_addr = 0, | |
28 | .phy_if = PHY_INTERFACE_MODE_RMII, | |
29 | }, | |
30 | { | |
31 | .slave_reg_ofs = 0x308, | |
32 | .sliver_reg_ofs = 0xdc0, | |
33 | .phy_addr = 1, | |
34 | .phy_if = PHY_INTERFACE_MODE_RMII, | |
35 | ||
36 | }, | |
37 | }; | |
38 | ||
39 | static struct cpsw_platform_data cl_som_am57_cpsw_data = { | |
40 | .mdio_base = CPSW_MDIO_BASE, | |
41 | .cpsw_base = CPSW_BASE, | |
42 | .mdio_div = 0xff, | |
43 | .channels = 8, | |
44 | .cpdma_reg_ofs = 0x800, | |
45 | .slaves = 2, | |
46 | .slave_data = cl_som_am57x_cpsw_slaves, | |
47 | .ale_reg_ofs = 0xd00, | |
48 | .ale_entries = 1024, | |
49 | .host_port_reg_ofs = 0x108, | |
50 | .hw_stats_reg_ofs = 0x900, | |
51 | .bd_ram_ofs = 0x2000, | |
52 | .mac_control = (1 << 5), | |
53 | .control = cpsw_control, | |
54 | .host_port_num = 0, | |
55 | .version = CPSW_CTRL_VERSION_2, | |
56 | }; | |
57 | ||
58 | /* | |
59 | * cl_som_am57x_efuse_read_mac_addr() - read Ethernet port MAC address. | |
60 | * The information is retrieved from the SOC's registers. | |
61 | * @buff: read buffer. | |
62 | * @port_num: port number. | |
63 | */ | |
64 | static void cl_som_am57x_efuse_read_mac_addr(uchar *buff, uint port_num) | |
65 | { | |
66 | uint32_t mac_hi, mac_lo; | |
67 | ||
68 | if (port_num) { | |
69 | mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); | |
70 | mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); | |
71 | } else { | |
72 | mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); | |
73 | mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); | |
74 | } | |
75 | ||
76 | buff[0] = (mac_hi & 0xFF0000) >> 16; | |
77 | buff[1] = (mac_hi & 0xFF00) >> 8; | |
78 | buff[2] = mac_hi & 0xFF; | |
79 | buff[3] = (mac_lo & 0xFF0000) >> 16; | |
80 | buff[4] = (mac_lo & 0xFF00) >> 8; | |
81 | buff[5] = mac_lo & 0xFF; | |
82 | } | |
83 | ||
84 | /* | |
85 | * cl_som_am57x_handle_mac_address() - set MAC address in the U-Boot | |
86 | * environment. | |
87 | * The address is retrieved retrieved from an EEPROM field or from the | |
88 | * SOC's registers. | |
89 | * @env_name: U-Boot environment name. | |
90 | * @field_name: EEPROM field name. | |
91 | * @port_num: SOC's port number. | |
92 | */ | |
93 | static int cl_som_am57x_handle_mac_address(char *env_name, uint port_num) | |
94 | { | |
95 | int ret; | |
96 | uint8_t enetaddr[6]; | |
97 | ||
35affd7a | 98 | ret = eth_env_get_enetaddr(env_name, enetaddr); |
fc300e2c DL |
99 | if (ret) |
100 | return 0; | |
101 | ||
102 | ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); | |
103 | ||
104 | if (ret || !is_valid_ethaddr(enetaddr)) | |
105 | cl_som_am57x_efuse_read_mac_addr(enetaddr, port_num); | |
106 | ||
107 | if (!is_valid_ethaddr(enetaddr)) | |
108 | return -1; | |
109 | ||
fd1e959e | 110 | ret = eth_env_set_enetaddr(env_name, enetaddr); |
fc300e2c DL |
111 | if (ret) |
112 | printf("cl-som-am57x: Failed to set Eth port %d MAC address\n", | |
113 | port_num); | |
114 | ||
115 | return ret; | |
116 | } | |
117 | ||
118 | #define CL_SOM_AM57X_PHY_ADDR2 0x01 | |
119 | #define AR8033_PHY_DEBUG_ADDR_REG 0x1d | |
120 | #define AR8033_PHY_DEBUG_DATA_REG 0x1e | |
121 | #define AR8033_DEBUG_RGMII_RX_CLK_DLY_REG 0x00 | |
122 | #define AR8033_DEBUG_RGMII_TX_CLK_DLY_REG 0x05 | |
123 | #define AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK (1 << 15) | |
124 | #define AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK (1 << 8) | |
125 | ||
126 | /* | |
127 | * cl_som_am57x_rgmii_clk_delay() - Set RGMII clock delay. | |
128 | * Enable RX delay, disable TX delay. | |
129 | */ | |
130 | static void cl_som_am57x_rgmii_clk_delay(void) | |
131 | { | |
132 | uint16_t mii_reg_val; | |
133 | const char *devname; | |
134 | ||
135 | devname = miiphy_get_current_dev(); | |
136 | /* PHY 2 */ | |
137 | miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG, | |
138 | AR8033_DEBUG_RGMII_RX_CLK_DLY_REG); | |
139 | miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, | |
140 | &mii_reg_val); | |
141 | mii_reg_val |= AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK; | |
142 | miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, | |
143 | mii_reg_val); | |
144 | ||
145 | miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG, | |
146 | AR8033_DEBUG_RGMII_TX_CLK_DLY_REG); | |
147 | miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, | |
148 | &mii_reg_val); | |
149 | mii_reg_val &= ~AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK; | |
150 | miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG, | |
151 | mii_reg_val); | |
152 | } | |
153 | ||
154 | #define CL_SOM_AM57X_GPIO_PHY1_RST 92 /* GPIO3_28 */ | |
155 | #define CL_SOM_AM57X_RGMII_PORT1 1 | |
156 | ||
157 | int board_eth_init(bd_t *bis) | |
158 | { | |
159 | int ret; | |
160 | uint32_t ctrl_val; | |
161 | char *cpsw_phy_envval; | |
162 | int cpsw_act_phy = 1; | |
163 | ||
164 | /* SB-SOM-AM57x primary Eth (P21) is routed to RGMII1 */ | |
165 | ret = cl_som_am57x_handle_mac_address("ethaddr", | |
166 | CL_SOM_AM57X_RGMII_PORT1); | |
167 | ||
168 | if (ret) | |
169 | return -1; | |
170 | ||
171 | /* Select RGMII for GMII1_SEL */ | |
172 | ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); | |
173 | ctrl_val |= 0x22; | |
174 | writel(ctrl_val, (*ctrl)->control_core_control_io1); | |
175 | mdelay(10); | |
176 | ||
177 | gpio_request(CL_SOM_AM57X_GPIO_PHY1_RST, "phy1_rst"); | |
178 | gpio_direction_output(CL_SOM_AM57X_GPIO_PHY1_RST, 0); | |
179 | mdelay(20); | |
180 | ||
181 | gpio_set_value(CL_SOM_AM57X_GPIO_PHY1_RST, 1); | |
182 | mdelay(20); | |
183 | ||
00caae6d | 184 | cpsw_phy_envval = env_get("cpsw_phy"); |
fc300e2c DL |
185 | if (cpsw_phy_envval != NULL) |
186 | cpsw_act_phy = simple_strtoul(cpsw_phy_envval, NULL, 0); | |
187 | ||
188 | cl_som_am57_cpsw_data.active_slave = cpsw_act_phy; | |
189 | ||
190 | ret = cpsw_register(&cl_som_am57_cpsw_data); | |
191 | if (ret < 0) | |
192 | printf("Error %d registering CPSW switch\n", ret); | |
193 | ||
194 | /* Set RGMII clock delay */ | |
195 | cl_som_am57x_rgmii_clk_delay(); | |
196 | ||
197 | return ret; | |
198 | } |