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Commit | Line | Data |
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8883ddaf | 1 | /* |
5dc5a8ca | 2 | * Copyright (C) 2016 Compulab, Ltd. |
8883ddaf NK |
3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8883ddaf | 8 | #include <spl.h> |
43e568c4 | 9 | #include <i2c.h> |
8883ddaf | 10 | #include <asm/arch/clock.h> |
8883ddaf | 11 | #include <asm/arch/ddr_defs.h> |
8883ddaf | 12 | #include <asm/gpio.h> |
43e568c4 NK |
13 | #include <power/pmic.h> |
14 | #include <power/tps65218.h> | |
15 | #include "board.h" | |
8883ddaf NK |
16 | |
17 | DECLARE_GLOBAL_DATA_PTR; | |
18 | ||
8883ddaf NK |
19 | const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 }; |
20 | const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 }; | |
21 | const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 }; | |
22 | const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 }; | |
23 | ||
24 | const struct ctrl_ioregs ioregs_ddr3 = { | |
25 | .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, | |
26 | .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, | |
27 | .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, | |
28 | .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, | |
29 | .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, | |
30 | .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, | |
31 | .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, | |
32 | .emif_sdram_config_ext = 0x0143, | |
33 | }; | |
34 | ||
35 | /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ | |
36 | struct emif_regs ddr3_emif_regs = { | |
37 | .sdram_config = 0x638413B2, | |
38 | .ref_ctrl = 0x00000C30, | |
39 | .sdram_tim1 = 0xEAAAD4DB, | |
40 | .sdram_tim2 = 0x266B7FDA, | |
41 | .sdram_tim3 = 0x107F8678, | |
42 | .read_idle_ctrl = 0x00050000, | |
43 | .zq_config = 0x50074BE4, | |
44 | .temp_alert_config = 0x0, | |
45 | .emif_ddr_phy_ctlr_1 = 0x0E004008, | |
46 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, | |
47 | .emif_ddr_ext_phy_ctrl_2 = 0x00000066, | |
48 | .emif_ddr_ext_phy_ctrl_3 = 0x00000091, | |
49 | .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, | |
50 | .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, | |
51 | .emif_rd_wr_exec_thresh = 0x80000405, | |
52 | .emif_prio_class_serv_map = 0x80000001, | |
53 | .emif_connect_id_serv_1_map = 0x80000094, | |
54 | .emif_connect_id_serv_2_map = 0x00000000, | |
55 | .emif_cos_config = 0x000FFFFF | |
56 | }; | |
57 | ||
58 | const u32 ext_phy_ctrl_const_base_ddr3[] = { | |
59 | 0x00000000, | |
60 | 0x00000044, | |
61 | 0x00000044, | |
62 | 0x00000046, | |
63 | 0x00000046, | |
64 | 0x00000000, | |
65 | 0x00000059, | |
66 | 0x00000077, | |
67 | 0x00000093, | |
68 | 0x000000A8, | |
69 | 0x00000000, | |
70 | 0x00000019, | |
71 | 0x00000037, | |
72 | 0x00000053, | |
73 | 0x00000068, | |
74 | 0x00000000, | |
75 | 0x0, | |
76 | 0x0, | |
77 | 0x40000000, | |
78 | 0x08102040 | |
79 | }; | |
80 | ||
81 | void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) | |
82 | { | |
83 | *regs = ext_phy_ctrl_const_base_ddr3; | |
84 | *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); | |
85 | } | |
86 | ||
87 | const struct dpll_params *get_dpll_ddr_params(void) | |
88 | { | |
89 | return &dpll_ddr; | |
90 | } | |
91 | ||
92 | const struct dpll_params *get_dpll_mpu_params(void) | |
93 | { | |
94 | return &dpll_mpu; | |
95 | } | |
96 | ||
97 | const struct dpll_params *get_dpll_core_params(void) | |
98 | { | |
99 | return &dpll_core; | |
100 | } | |
101 | ||
102 | const struct dpll_params *get_dpll_per_params(void) | |
103 | { | |
104 | return &dpll_per; | |
105 | } | |
106 | ||
43e568c4 NK |
107 | void scale_vcores(void) |
108 | { | |
109 | set_i2c_pin_mux(); | |
110 | i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); | |
111 | if (i2c_probe(TPS65218_CHIP_PM)) | |
112 | return; | |
113 | ||
114 | tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV); | |
115 | tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV); | |
116 | } | |
117 | ||
8883ddaf NK |
118 | void sdram_init(void) |
119 | { | |
120 | unsigned long ram_size; | |
121 | ||
8883ddaf NK |
122 | config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); |
123 | ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); | |
124 | if (ram_size == 0x80000000 || | |
125 | ram_size == 0x40000000 || | |
126 | ram_size == 0x20000000) | |
127 | return; | |
128 | ||
129 | ddr3_emif_regs.sdram_config = 0x638453B2; | |
130 | config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); | |
131 | ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); | |
132 | if (ram_size == 0x08000000) | |
133 | return; | |
134 | ||
135 | hang(); | |
136 | } | |
8883ddaf | 137 |