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clk: clk_stm32f7: fix PLL clock division factor
[people/ms/u-boot.git] / board / congatec / Kconfig
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1#
2# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3#
4# SPDX-License-Identifier: GPL-2.0+
5#
6
7if VENDOR_CONGATEC
8
9choice
10 prompt "Mainboard model"
11 optional
12
13config TARGET_CONGA_QEVAL20_QA3_E3845
14 bool "congatec QEVAL 2.0 & conga-QA3/E3845"
e5ec4815 15 select BOARD_LATE_INIT
fedb428c 16 imply SCSI
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17 help
18 This is the congatec Qseven 2.0 evaluation carrier board
19 (conga-QEVAL) equipped with the conga-QA3/E3845-4G SoM.
20 It contains an Atom E3845 with Ethernet, micro-SD, USB 2,
21 USB 3, SATA, serial console and HDMI 1.3 video out.
22 It requires some binary blobs - see README.x86 for details.
23
24 Note that PCIE_ECAM_BASE is set up by the FSP so the value used
25 by U-Boot matches that value.
26
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27config TARGET_THEADORABLE_X86_CONGA_QA3_E3845
28 bool "theadorable-x86 baseboard & conga-QA3/E3845"
29 help
30 This is the theadorable-x86 baseboard board equipped with the
31 conga-QA3/E3845-4G SoM. It contains an Atom E3845 with Ethernet,
32 micro-SD, USB 2, USB 3, SATA, serial console and HDMI 1.3 video
33 out. It requires some binary blobs - see README.x86 for details.
34
35 Note that PCIE_ECAM_BASE is set up by the FSP so the value used
36 by U-Boot matches that value.
37
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38endchoice
39
40source "board/congatec/conga-qeval20-qa3-e3845/Kconfig"
41
42endif