[people/ms/u-boot.git] / board / cpc45 / cpc45.c

/*
 * (C) Copyright 2001
 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc824x.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#include <i2c.h>

int sysControlDisplay(int digit, uchar ascii_code);
extern void Plx9030Init(void);
extern void SPD67290Init(void);

	/* We have to clear the initial data area here. Couldn't have done it
	 * earlier because DRAM had not been initialized.
	 */
int board_early_init_f(void)
{

	/* enable DUAL UART Mode on CPC45 */
	*(uchar*)DUART_DCR |= 0x1;	/* set DCM bit */

	return 0;
}

int checkboard(void)
{
/*
	char  revision = BOARD_REV;
*/
	ulong busfreq  = get_bus_freq(0);
	char  buf[32];

	puts ("CPC45  ");
/*
	printf("Revision %d ", revision);
*/
	printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));

	return 0;
}

phys_size_t initdram (int board_type)
{
	int m, row, col, bank, i, ref;
	unsigned long start, end;
	uint32_t mccr1, mccr2;
	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
	uint8_t mber = 0;
	unsigned int tmp;

	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);

	if (i2c_reg_read (0x50, 2) != 0x04)
		return 0;	/* Memory type */

	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
	row = i2c_reg_read (0x50, 3);	/* # of rows */
	col = i2c_reg_read (0x50, 4);	/* # of columns */
	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
	ref  = i2c_reg_read (0x50, 12);	/* refresh rate / type */

	CONFIG_READ_WORD(MCCR1, mccr1);
	mccr1 &= 0xffff0000;

	CONFIG_READ_WORD(MCCR2, mccr2);
	mccr2 &= 0xffff0000;

	start = CFG_SDRAM_BASE;
	end = start + (1 << (col + row + 3) ) * bank - 1;

	for (i = 0; i < m; i++) {
		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
		if (i < 4) {
			msar1  |= ((start >> 20) & 0xff) << i * 8;
			emsar1 |= ((start >> 28) & 0xff) << i * 8;
			mear1  |= ((end >> 20) & 0xff) << i * 8;
			emear1 |= ((end >> 28) & 0xff) << i * 8;
		} else {
			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
		}
		mber |= 1 << i;
		start += (1 << (col + row + 3) ) * bank;
		end += (1 << (col + row + 3) ) * bank;
	}
	for (; i < 8; i++) {
		if (i < 4) {
			msar1  |= 0xff << i * 8;
			emsar1 |= 0x30 << i * 8;
			mear1  |= 0xff << i * 8;
			emear1 |= 0x30 << i * 8;
		} else {
			msar2  |= 0xff << (i-4) * 8;
			emsar2 |= 0x30 << (i-4) * 8;
			mear2  |= 0xff << (i-4) * 8;
			emear2 |= 0x30 << (i-4) * 8;
		}
	}

	switch(ref) {
		case 0x00:
		case 0x80:
			tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
			break;
		case 0x01:
		case 0x81:
			tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
			break;
		case 0x02:
		case 0x82:
			tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
			break;
		case 0x03:
		case 0x83:
			tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
			break;
		case 0x04:
		case 0x84:
			tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
			break;
		case 0x05:
		case 0x85:
			tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
			break;
		default:
			tmp = 0x512;
			break;
	}

	CONFIG_WRITE_WORD(MCCR1, mccr1);
	CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
	CONFIG_WRITE_WORD(MSAR1, msar1);
	CONFIG_WRITE_WORD(EMSAR1, emsar1);
	CONFIG_WRITE_WORD(MEAR1, mear1);
	CONFIG_WRITE_WORD(EMEAR1, emear1);
	CONFIG_WRITE_WORD(MSAR2, msar2);
	CONFIG_WRITE_WORD(EMSAR2, emsar2);
	CONFIG_WRITE_WORD(MEAR2, mear2);
	CONFIG_WRITE_WORD(EMEAR2, emear2);
	CONFIG_WRITE_BYTE(MBER, mber);

	return (1 << (col + row + 3) ) * bank * m;
}


/*
 * Initialize PCI Devices, report devices found.
 */

static struct pci_config_table pci_cpc45_config_table[] = {
#ifndef CONFIG_PCI_PNP
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
				       PCI_ENET0_MEMADDR,
				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
	  pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
				       PCI_PLX9030_MEMADDR,
				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID,
	  pci_cfgfunc_config_device, { PCMCIA_IO_BASE,
				       PCMCIA_IO_BASE,
				       PCI_COMMAND_MEMORY | PCI_COMMAND_IO }},
#endif /*CONFIG_PCI_PNP*/
	{ }
};

struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
	config_table: pci_cpc45_config_table,
#endif
};

void pci_init_board(void)
{
	pci_mpc824x_init(&hose);

	/* init PCI_to_LOCAL Bus BRIDGE */
	Plx9030Init();

	/* Clear Display */
	DISP_CWORD = 0x0;

	sysControlDisplay(0,' ');
	sysControlDisplay(1,'C');
	sysControlDisplay(2,'P');
	sysControlDisplay(3,'C');
	sysControlDisplay(4,' ');
	sysControlDisplay(5,'4');
	sysControlDisplay(6,'5');
	sysControlDisplay(7,' ');

}

/**************************************************************************
*
* sysControlDisplay - controls one of the Alphanum. Display digits.
*
* This routine will write an ASCII character to the display digit requested.
*
* SEE ALSO:
*
* RETURNS: NA
*/

int sysControlDisplay (int digit,	/* number of digit 0..7 */
		       uchar ascii_code	/* ASCII code */
		      )
{
	if ((digit < 0) || (digit > 7))
		return (-1);

	*((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;

	return (0);
}

#if defined(CONFIG_CMD_PCMCIA)

#ifdef CFG_PCMCIA_MEM_ADDR
volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
#endif

int pcmcia_init(void)
{
	u_int rc;

	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");

	rc = i82365_init();

	return rc;
}

#endif

# ifdef CONFIG_IDE_LED
void ide_led (uchar led, uchar status)
{
	u_char  val;
	/* We have one PCMCIA slot and use LED H4 for the IDE Interface */
	val = readb(BCSR_BASE + 0x04);
	if (status) {				/* led on */
		val |= B_CTRL_LED0;
	} else {
		val &= ~B_CTRL_LED0;
	}
	writeb(val, BCSR_BASE + 0x04);
}
# endif
Commit	Line	Data
3bac3513 WD	1	/*
	2	* (C) Copyright 2001
	3	* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <mpc824x.h>
	26	#include <asm/processor.h>
e2ffd59b	27	#include <asm/io.h>
3bac3513	28	#include <pci.h>
49822e23	29	#include <i2c.h>
3bac3513	30
8bde7f77	31	int sysControlDisplay(int digit, uchar ascii_code);
3bac3513	32	extern void Plx9030Init(void);
e2ffd59b	33	extern void SPD67290Init(void);
3bac3513 WD	34
	35	/* We have to clear the initial data area here. Couldn't have done it
	36	* earlier because DRAM had not been initialized.
	37	*/
c837dcb1	38	int board_early_init_f(void)
3bac3513 WD	39	{
	40
	41	/* enable DUAL UART Mode on CPC45 */
	42	(uchar)DUART_DCR \|= 0x1; /* set DCM bit */
	43
	44	return 0;
	45	}
	46
	47	int checkboard(void)
	48	{
	49	/*
	50	char revision = BOARD_REV;
	51	*/
	52	ulong busfreq = get_bus_freq(0);
	53	char buf[32];
	54
d7a04603	55	puts ("CPC45 ");
3bac3513 WD	56	/*
	57	printf("Revision %d ", revision);
	58	*/
	59	printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
	60
	61	return 0;
	62	}
	63
9973e3c6	64	phys_size_t initdram (int board_type)
3bac3513	65	{
49822e23 WD	66	int m, row, col, bank, i, ref;
	67	unsigned long start, end;
	68	uint32_t mccr1, mccr2;
	69	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
	70	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
	71	uint8_t mber = 0;
	72	unsigned int tmp;
	73
	74	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
	75
	76	if (i2c_reg_read (0x50, 2) != 0x04)
	77	return 0; /* Memory type */
	78
	79	m = i2c_reg_read (0x50, 5); /* # of physical banks */
	80	row = i2c_reg_read (0x50, 3); /* # of rows */
	81	col = i2c_reg_read (0x50, 4); /* # of columns */
	82	bank = i2c_reg_read (0x50, 17); /* # of logical banks */
	83	ref = i2c_reg_read (0x50, 12); /* refresh rate / type */
	84
	85	CONFIG_READ_WORD(MCCR1, mccr1);
	86	mccr1 &= 0xffff0000;
	87
	88	CONFIG_READ_WORD(MCCR2, mccr2);
	89	mccr2 &= 0xffff0000;
	90
	91	start = CFG_SDRAM_BASE;
	92	end = start + (1 << (col + row + 3) ) * bank - 1;
	93
	94	for (i = 0; i < m; i++) {
	95	mccr1 \|= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
	96	if (i < 4) {
	97	msar1 \|= ((start >> 20) & 0xff) << i * 8;
	98	emsar1 \|= ((start >> 28) & 0xff) << i * 8;
	99	mear1 \|= ((end >> 20) & 0xff) << i * 8;
	100	emear1 \|= ((end >> 28) & 0xff) << i * 8;
	101	} else {
	102	msar2 \|= ((start >> 20) & 0xff) << (i-4) * 8;
	103	emsar2 \|= ((start >> 28) & 0xff) << (i-4) * 8;
	104	mear2 \|= ((end >> 20) & 0xff) << (i-4) * 8;
	105	emear2 \|= ((end >> 28) & 0xff) << (i-4) * 8;
	106	}
	107	mber \|= 1 << i;
	108	start += (1 << (col + row + 3) ) * bank;
	109	end += (1 << (col + row + 3) ) * bank;
	110	}
	111	for (; i < 8; i++) {
	112	if (i < 4) {
	113	msar1 \|= 0xff << i * 8;
	114	emsar1 \|= 0x30 << i * 8;
	115	mear1 \|= 0xff << i * 8;
	116	emear1 \|= 0x30 << i * 8;
	117	} else {
	118	msar2 \|= 0xff << (i-4) * 8;
	119	emsar2 \|= 0x30 << (i-4) * 8;
	120	mear2 \|= 0xff << (i-4) * 8;
	121	emear2 \|= 0x30 << (i-4) * 8;
	122	}
	123	}
	124
	125	switch(ref) {
	126	case 0x00:
	127	case 0x80:
	128	tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
	129	break;
130	case 0x01:
131	case 0x81:
132	tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
133	break;
134	case 0x02:
135	case 0x82:
136	tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
137	break;
138	case 0x03:
139	case 0x83:
140	tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
141	break;
142	case 0x04:
143	case 0x84:
144	tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
145	break;
146	case 0x05:
147	case 0x85:
148	tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
149	break;
150	default:
151	tmp = 0x512;
152	break;
153	}
154
155	CONFIG_WRITE_WORD(MCCR1, mccr1);
156	CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
157	CONFIG_WRITE_WORD(MSAR1, msar1);
158	CONFIG_WRITE_WORD(EMSAR1, emsar1);
159	CONFIG_WRITE_WORD(MEAR1, mear1);
160	CONFIG_WRITE_WORD(EMEAR1, emear1);
161	CONFIG_WRITE_WORD(MSAR2, msar2);
162	CONFIG_WRITE_WORD(EMSAR2, emsar2);
163	CONFIG_WRITE_WORD(MEAR2, mear2);
164	CONFIG_WRITE_WORD(EMEAR2, emear2);
165	CONFIG_WRITE_BYTE(MBER, mber);
166
167	return (1 << (col + row + 3) ) * bank * m;
3bac3513 WD	168	}
3bac3513 WD	169
49822e23	170
3bac3513 WD	171	/*
	172	* Initialize PCI Devices, report devices found.
	173	*/
3bac3513	174
49822e23 WD	175	static struct pci_config_table pci_cpc45_config_table[] = {
	176	#ifndef CONFIG_PCI_PNP
	177	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
3bac3513 WD	178	pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
	179	PCI_ENET0_MEMADDR,
	180	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER }},
49822e23 WD	181	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
	182	pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
	183	PCI_PLX9030_MEMADDR,
	184	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER }},
e2ffd59b WD	185	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID,
	186	pci_cfgfunc_config_device, { PCMCIA_IO_BASE,
	187	PCMCIA_IO_BASE,
	188	PCI_COMMAND_MEMORY \| PCI_COMMAND_IO }},
49822e23	189	#endif /CONFIG_PCI_PNP/
3bac3513 WD	190	{ }
3bac3513 WD	191	};
3bac3513 WD	192
	193	struct pci_controller hose = {
	194	#ifndef CONFIG_PCI_PNP
49822e23	195	config_table: pci_cpc45_config_table,
3bac3513 WD	196	#endif
	197	};
	198
	199	void pci_init_board(void)
	200	{
	201	pci_mpc824x_init(&hose);
	202
	203	/* init PCI_to_LOCAL Bus BRIDGE */
	204	Plx9030Init();
	205
49822e23 WD	206	/* Clear Display */
	207	DISP_CWORD = 0x0;
	208
3bac3513 WD	209	sysControlDisplay(0,' ');
	210	sysControlDisplay(1,'C');
	211	sysControlDisplay(2,'P');
	212	sysControlDisplay(3,'C');
	213	sysControlDisplay(4,' ');
	214	sysControlDisplay(5,'4');
	215	sysControlDisplay(6,'5');
	216	sysControlDisplay(7,' ');
	217
	218	}
	219
	220	/**************************************************************************
	221	*
	222	* sysControlDisplay - controls one of the Alphanum. Display digits.
	223	*
	224	* This routine will write an ASCII character to the display digit requested.
	225	*
	226	* SEE ALSO:
	227	*
	228	* RETURNS: NA
	229	*/
	230
49822e23 WD	231	int sysControlDisplay (int digit, /* number of digit 0..7 */
	232	uchar ascii_code /* ASCII code */
	233	)
3bac3513 WD	234	{
	235	if ((digit < 0) \|\| (digit > 7))
	236	return (-1);
	237
49822e23	238	((volatile uchar ) (DISP_CHR_RAM + digit)) = ascii_code;
3bac3513 WD	239
	240	return (0);
	241	}
e2ffd59b	242
fcec2eb9	243	#if defined(CONFIG_CMD_PCMCIA)
e2ffd59b WD	244
	245	#ifdef CFG_PCMCIA_MEM_ADDR
	246	volatile unsigned char pcmcia_mem = (unsigned char)CFG_PCMCIA_MEM_ADDR;
	247	#endif
	248
	249	int pcmcia_init(void)
	250	{
	251	u_int rc;
	252
	253	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
	254
	255	rc = i82365_init();
	256
	257	return rc;
	258	}
	259
77a31854	260	#endif
e2ffd59b WD	261
	262	# ifdef CONFIG_IDE_LED
	263	void ide_led (uchar led, uchar status)
	264	{
	265	u_char val;
	266	/* We have one PCMCIA slot and use LED H4 for the IDE Interface */
	267	val = readb(BCSR_BASE + 0x04);
	268	if (status) { /* led on */
	269	val \|= B_CTRL_LED0;
	270	} else {
	271	val &= ~B_CTRL_LED0;
	272	}
	273	writeb(val, BCSR_BASE + 0x04);
	274	}
	275	# endif