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384cc687 WD |
1 | /* |
2 | * (C) Copyright 2001-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <ioports.h> | |
26 | #include <mpc8260.h> | |
27 | #include "cpu87.h" | |
28 | #include <pci.h> | |
10efa024 | 29 | #include <netdev.h> |
384cc687 WD |
30 | |
31 | /* | |
32 | * I/O Port configuration table | |
33 | * | |
34 | * if conf is 1, then that port pin will be configured at boot time | |
35 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
36 | */ | |
37 | ||
38 | const iop_conf_t iop_conf_tab[4][32] = { | |
39 | ||
40 | /* Port A configuration */ | |
41 | { /* conf ppar psor pdir podr pdat */ | |
42 | /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ | |
43 | /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ | |
44 | /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ | |
45 | /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ | |
46 | /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ | |
47 | /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ | |
48 | /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */ | |
49 | /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */ | |
50 | /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */ | |
51 | /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */ | |
52 | /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ | |
53 | /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ | |
54 | /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ | |
55 | /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ | |
56 | /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ | |
57 | /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ | |
58 | /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ | |
59 | /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ | |
60 | /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */ | |
61 | /* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */ | |
62 | /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */ | |
63 | /* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */ | |
64 | /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ | |
65 | /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ | |
66 | /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ | |
67 | /* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */ | |
68 | /* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */ | |
69 | /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */ | |
70 | /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */ | |
71 | /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ | |
72 | /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */ | |
73 | /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */ | |
74 | }, | |
75 | ||
76 | /* Port B configuration */ | |
77 | { /* conf ppar psor pdir podr pdat */ | |
78 | /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ | |
79 | /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ | |
80 | /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ | |
81 | /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ | |
82 | /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ | |
83 | /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ | |
84 | /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ | |
85 | /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ | |
86 | /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ | |
87 | /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ | |
88 | /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ | |
89 | /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ | |
90 | /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ | |
91 | /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ | |
92 | /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ | |
93 | /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ | |
94 | /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ | |
95 | /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ | |
96 | /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ | |
97 | /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ | |
98 | /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ | |
99 | /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ | |
100 | /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ | |
101 | /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ | |
102 | /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ | |
103 | /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ | |
104 | /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ | |
105 | /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ | |
106 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */ | |
107 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */ | |
108 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */ | |
109 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */ | |
110 | }, | |
111 | ||
112 | /* Port C */ | |
113 | { /* conf ppar psor pdir podr pdat */ | |
114 | /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ | |
115 | /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ | |
116 | /* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */ | |
117 | /* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */ | |
118 | /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ | |
119 | /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ | |
120 | /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ | |
121 | /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ | |
122 | /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */ | |
123 | /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */ | |
124 | /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ | |
125 | /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ | |
126 | /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ | |
127 | /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ | |
128 | /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ | |
129 | /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ | |
130 | /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ | |
131 | /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ | |
132 | /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ | |
133 | /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ | |
134 | /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ | |
135 | /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ | |
136 | /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */ | |
137 | /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ | |
138 | /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ | |
139 | /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ | |
140 | /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ | |
141 | /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ | |
142 | /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ | |
143 | /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ | |
144 | /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ | |
145 | /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */ | |
146 | }, | |
147 | ||
148 | /* Port D */ | |
149 | { /* conf ppar psor pdir podr pdat */ | |
150 | /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */ | |
151 | /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */ | |
152 | /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */ | |
153 | /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */ | |
154 | /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */ | |
155 | /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */ | |
156 | /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ | |
157 | /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ | |
158 | /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ | |
159 | /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ | |
160 | /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ | |
161 | /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ | |
162 | /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ | |
163 | /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ | |
164 | /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ | |
165 | /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ | |
166 | #if defined(CONFIG_SOFT_I2C) | |
167 | /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ | |
168 | /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ | |
169 | #else | |
170 | #if defined(CONFIG_HARD_I2C) | |
171 | /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ | |
172 | /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ | |
173 | #else /* normal I/O port pins */ | |
174 | /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ | |
175 | /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ | |
176 | #endif | |
177 | #endif | |
178 | /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ | |
179 | /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ | |
180 | /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ | |
181 | /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ | |
182 | /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ | |
183 | /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ | |
184 | /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ | |
185 | /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ | |
186 | /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ | |
187 | /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ | |
188 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */ | |
189 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */ | |
190 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */ | |
191 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */ | |
192 | } | |
193 | }; | |
194 | ||
195 | /* ------------------------------------------------------------------------- */ | |
196 | ||
197 | /* Check Board Identity: | |
198 | */ | |
199 | int checkboard (void) | |
200 | { | |
fd27996d | 201 | printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f); |
384cc687 WD |
202 | return 0; |
203 | } | |
204 | ||
205 | /* ------------------------------------------------------------------------- */ | |
206 | ||
207 | /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx | |
208 | * | |
209 | * This routine performs standard 8260 initialization sequence | |
210 | * and calculates the available memory size. It may be called | |
211 | * several times to try different SDRAM configurations on both | |
212 | * 60x and local buses. | |
213 | */ | |
214 | static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, | |
215 | ulong orx, volatile uchar * base) | |
216 | { | |
217 | volatile uchar c = 0xff; | |
218 | volatile uint *sdmr_ptr; | |
219 | volatile uint *orx_ptr; | |
220 | ulong maxsize, size; | |
221 | int i; | |
222 | ||
223 | /* We must be able to test a location outsize the maximum legal size | |
224 | * to find out THAT we are outside; but this address still has to be | |
225 | * mapped by the controller. That means, that the initial mapping has | |
226 | * to be (at least) twice as large as the maximum expected size. | |
227 | */ | |
228 | maxsize = (1 + (~orx | 0x7fff)) / 2; | |
229 | ||
230 | /* Since CFG_SDRAM_BASE is always 0 (??), we assume that | |
231 | * we are configuring CS1 if base != 0 | |
232 | */ | |
233 | sdmr_ptr = &memctl->memc_psdmr; | |
234 | orx_ptr = &memctl->memc_or2; | |
235 | ||
236 | *orx_ptr = orx; | |
237 | ||
238 | /* | |
239 | * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): | |
240 | * | |
241 | * "At system reset, initialization software must set up the | |
242 | * programmable parameters in the memory controller banks registers | |
243 | * (ORx, BRx, P/LSDMR). After all memory parameters are configured, | |
244 | * system software should execute the following initialization sequence | |
245 | * for each SDRAM device. | |
246 | * | |
247 | * 1. Issue a PRECHARGE-ALL-BANKS command | |
248 | * 2. Issue eight CBR REFRESH commands | |
249 | * 3. Issue a MODE-SET command to initialize the mode register | |
250 | * | |
251 | * The initial commands are executed by setting P/LSDMR[OP] and | |
252 | * accessing the SDRAM with a single-byte transaction." | |
253 | * | |
254 | * The appropriate BRx/ORx registers have already been set when we | |
255 | * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. | |
256 | */ | |
257 | ||
258 | *sdmr_ptr = sdmr | PSDMR_OP_PREA; | |
259 | *base = c; | |
260 | ||
261 | *sdmr_ptr = sdmr | PSDMR_OP_CBRR; | |
262 | for (i = 0; i < 8; i++) | |
263 | *base = c; | |
264 | ||
265 | *sdmr_ptr = sdmr | PSDMR_OP_MRW; | |
266 | *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ | |
267 | ||
268 | *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; | |
269 | *base = c; | |
270 | ||
271 | size = get_ram_size((long *)base, maxsize); | |
272 | ||
273 | *orx_ptr = orx | ~(size - 1); | |
274 | ||
275 | return (size); | |
276 | } | |
277 | ||
9973e3c6 | 278 | phys_size_t initdram (int board_type) |
384cc687 WD |
279 | { |
280 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
281 | volatile memctl8260_t *memctl = &immap->im_memctl; | |
282 | ||
283 | #ifndef CFG_RAMBOOT | |
fd27996d | 284 | ulong size8, size9, size10; |
384cc687 WD |
285 | #endif |
286 | long psize; | |
287 | ||
288 | psize = 32 * 1024 * 1024; | |
289 | ||
290 | memctl->memc_mptpr = CFG_MPTPR; | |
291 | memctl->memc_psrt = CFG_PSRT; | |
292 | ||
293 | #ifndef CFG_RAMBOOT | |
294 | /* 60x SDRAM setup: | |
295 | */ | |
296 | size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, | |
297 | (uchar *) CFG_SDRAM_BASE); | |
16850919 | 298 | |
384cc687 WD |
299 | size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, |
300 | (uchar *) CFG_SDRAM_BASE); | |
16850919 | 301 | |
fd27996d WD |
302 | size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL, |
303 | (uchar *) CFG_SDRAM_BASE); | |
16850919 | 304 | |
fd27996d | 305 | psize = max(size8,max(size9,size10)); |
16850919 | 306 | |
fd27996d | 307 | if (psize == size8) { |
384cc687 WD |
308 | psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, |
309 | (uchar *) CFG_SDRAM_BASE); | |
310 | printf ("(60x:8COL) "); | |
fd27996d WD |
311 | } else if (psize == size9){ |
312 | psize = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, | |
313 | (uchar *) CFG_SDRAM_BASE); | |
314 | printf ("(60x:9COL) "); | |
315 | } else | |
316 | printf ("(60x:10COL) "); | |
384cc687 WD |
317 | |
318 | #endif /* CFG_RAMBOOT */ | |
319 | ||
320 | icache_enable (); | |
321 | ||
322 | return (psize); | |
323 | } | |
324 | ||
fcec2eb9 | 325 | #if defined(CONFIG_CMD_DOC) |
384cc687 WD |
326 | extern void doc_probe (ulong physadr); |
327 | void doc_init (void) | |
328 | { | |
329 | doc_probe (CFG_DOC_BASE); | |
330 | } | |
331 | #endif | |
332 | ||
333 | #ifdef CONFIG_PCI | |
334 | struct pci_controller hose; | |
335 | ||
336 | extern void pci_mpc8250_init(struct pci_controller *); | |
337 | ||
338 | void pci_init_board(void) | |
339 | { | |
340 | pci_mpc8250_init(&hose); | |
341 | } | |
342 | #endif | |
10efa024 BW |
343 | |
344 | int board_eth_init(bd_t *bis) | |
345 | { | |
346 | return pci_eth_init(bis); | |
347 | } |