[thirdparty/u-boot.git] / board / csb272 / init.S

/*
 * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
 */
#include <config.h>
#include <asm/ppc4xx.h>

#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

#define LI32(reg,val) \
	addis   reg,0,val@h;\
	ori     reg,reg,val@l

#define WDCR_EBC(reg,val) \
	addi    r4,0,reg;\
	mtdcr   EBC0_CFGADDR,r4;\
	addis   r4,0,val@h;\
	ori     r4,r4,val@l;\
	mtdcr   EBC0_CFGDATA,r4

#define WDCR_SDRAM(reg,val) \
	addi    r4,0,reg;\
	mtdcr   SDRAM0_CFGADDR,r4;\
	addis   r4,0,val@h;\
	ori     r4,r4,val@l;\
	mtdcr   SDRAM0_CFGDATA,r4

/******************************************************************************
 * Function:	ext_bus_cntlr_init
 *
 * Description:	Configures EBC Controller and a few basic chip selects.
 *
 *		CS0 is setup to get the Boot Flash out of the addresss range
 *		so that we may setup a stack.  CS7 is setup so that we can
 *		access and reset the hardware watchdog.
 *
 *		IMPORTANT: For pass1 this code must run from
 *		cache since you can not reliably change a peripheral banks
 *		timing register (pbxap) while running code from that bank.
 *		For ex., since we are running from ROM on bank 0, we can NOT
 *		execute the code that modifies bank 0 timings from ROM, so
 *		we run it from cache.
 *
 * Notes:	Does NOT use the stack.
 *****************************************************************************/
	.section ".text"
	.align	2
	.globl	ext_bus_cntlr_init
	.type	ext_bus_cntlr_init, @function
ext_bus_cntlr_init:
	mflr	r0
	/********************************************************************
	 * Prefetch entire ext_bus_cntrl_init function into the icache.
	 * This is necessary because we are going to change the same CS we
	 * are executing from.  Otherwise a CPU lockup may occur.
	 *******************************************************************/
	bl	..getAddr
..getAddr:
	mflr	r3			/* get address of ..getAddr */

	/* Calculate number of cache lines for this function */
	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
	mtctr	r4
..ebcloop:
	icbt	r0, r3			/* prefetch cache line for addr in r3*/
	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
	bdnz	..ebcloop		/* continue for $CTR cache lines */

	/********************************************************************
	 * Delay to ensure all accesses to ROM are complete before changing
	 * bank 0 timings. 200usec should be enough.
	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
	 *******************************************************************/
	addis	r3, 0, 0x0
	ori	r3, r3, 0xA000		/* wait 200us from reset */
	mtctr	r3
..spinlp:
	bdnz	..spinlp		/* spin loop */

	/********************************************************************
	 * SETUP CPC0_CR0
	 *******************************************************************/
	LI32(r4, 0x007000c0)
	mtdcr	CPC0_CR0, r4

	/********************************************************************
	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
	 *******************************************************************/
	mfdcr	r4, CPC0_CR1
	ori	r4, r4, 0x4000
	mtdcr	CPC0_CR1, r4

	/********************************************************************
	 * Setup External Bus Controller (EBC).
	 *******************************************************************/
	WDCR_EBC(EBC0_CFG, 0xd84c0000)
	/********************************************************************
	 * Memory Bank 0 (Intel 28F128J3 Flash) initialization
	 *******************************************************************/
	/*WDCR_EBC(PB1AP, 0x02869200)*/
	WDCR_EBC(PB1AP, 0x07869200)
	WDCR_EBC(PB0CR, 0xfe0bc000)
	/********************************************************************
	 * Memory Bank 1 (Holtek HT6542B PS/2) initialization
	 *******************************************************************/
	WDCR_EBC(PB1AP, 0x1f869200)
	WDCR_EBC(PB1CR, 0xf0818000)
	/********************************************************************
	 * Memory Bank 2 (Epson S1D13506) initialization
	 *******************************************************************/
	WDCR_EBC(PB2AP, 0x05860300)
	WDCR_EBC(PB2CR, 0xf045a000)
	/********************************************************************
	 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
	 *******************************************************************/
	WDCR_EBC(PB3AP, 0x0387d200)
	WDCR_EBC(PB3CR, 0xf021c000)
	/********************************************************************
	 * Memory Bank 4-7 (Unused) initialization
	 *******************************************************************/
	WDCR_EBC(PB4AP, 0)
	WDCR_EBC(PB4CR, 0)
	WDCR_EBC(PB5AP, 0)
	WDCR_EBC(PB5CR, 0)
	WDCR_EBC(PB6AP, 0)
	WDCR_EBC(PB6CR, 0)
	WDCR_EBC(PB7AP, 0)
	WDCR_EBC(PB7CR, 0)

	/* We are all done */
	mtlr	r0			/* Restore link register */
	blr				/* Return to calling function */
.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
/* end ext_bus_cntlr_init() */

/******************************************************************************
 * Function:	sdram_init
 *
 * Description:	Configures SDRAM memory banks.
 *
 * Notes:	Does NOT use the stack.
 *****************************************************************************/
	.section ".text"
	.align	2
	.globl	sdram_init
	.type	sdram_init, @function
sdram_init:

	/*
	 * Disable memory controller to allow
	 * values to be changed.
	 */
	WDCR_SDRAM(SDRAM0_CFG, 0x00000000)

	/*
	 * Configure Memory Banks
	 */
	WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
	WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
	WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
	WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)

	/*
	 * Set up SDTR1 (SDRAM Timing Register)
	 */
	WDCR_SDRAM(SDRAM0_TR, 0x00854009)

	/*
	 * Set RTR (Refresh Timing Register)
	 */
	WDCR_SDRAM(SDRAM0_RTR,   0x10000000)
	/* WDCR_SDRAM(SDRAM0_RTR,   0x05f00000) */

	/********************************************************************
	 * Delay to ensure 200usec have elapsed since reset. Assume worst
	 * case that the core is running 200Mhz:
	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
	 *******************************************************************/
	addis   r3, 0, 0x0000
	ori     r3, r3, 0xA000		/* Wait >200us from reset */
	mtctr   r3
..spinlp2:
	bdnz    ..spinlp2		/* spin loop */

	/********************************************************************
	 * Set memory controller options reg, MCOPT1.
	 *******************************************************************/
	WDCR_SDRAM(SDRAM0_CFG,0x80800000)

..sdri_done:
	blr				/* Return to calling function */
.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
/* end sdram_init() */
Commit	Line	Data
46263f2d	1	/*
1b387ef5	2	* SPDX-License-Identifier: GPL-2.0 IBM-pibs
46263f2d	3	*/
cd0a9de6	4	#include <config.h>
b36df561	5	#include <asm/ppc4xx.h>
cd0a9de6 WD	6
	7	#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
	8
	9	#include <ppc_asm.tmpl>
	10	#include <ppc_defs.h>
	11
	12	#include <asm/cache.h>
	13	#include <asm/mmu.h>
	14
	15	#define LI32(reg,val) \
	16	addis reg,0,val@h;\
	17	ori reg,reg,val@l
	18
	19	#define WDCR_EBC(reg,val) \
	20	addi r4,0,reg;\
d1c3b275	21	mtdcr EBC0_CFGADDR,r4;\
cd0a9de6 WD	22	addis r4,0,val@h;\
cd0a9de6 WD	23	ori r4,r4,val@l;\
d1c3b275	24	mtdcr EBC0_CFGDATA,r4
cd0a9de6 WD	25
	26	#define WDCR_SDRAM(reg,val) \
	27	addi r4,0,reg;\
d1c3b275	28	mtdcr SDRAM0_CFGADDR,r4;\
cd0a9de6 WD	29	addis r4,0,val@h;\
cd0a9de6 WD	30	ori r4,r4,val@l;\
d1c3b275	31	mtdcr SDRAM0_CFGDATA,r4
cd0a9de6 WD	32
	33	/******************************************************************************
	34	* Function: ext_bus_cntlr_init
	35	*
	36	* Description: Configures EBC Controller and a few basic chip selects.
	37	*
	38	* CS0 is setup to get the Boot Flash out of the addresss range
	39	* so that we may setup a stack. CS7 is setup so that we can
	40	* access and reset the hardware watchdog.
	41	*
	42	* IMPORTANT: For pass1 this code must run from
	43	* cache since you can not reliably change a peripheral banks
	44	* timing register (pbxap) while running code from that bank.
	45	* For ex., since we are running from ROM on bank 0, we can NOT
	46	* execute the code that modifies bank 0 timings from ROM, so
	47	* we run it from cache.
	48	*
	49	* Notes: Does NOT use the stack.
	50	*****************************************************************************/
	51	.section ".text"
	52	.align 2
	53	.globl ext_bus_cntlr_init
	54	.type ext_bus_cntlr_init, @function
	55	ext_bus_cntlr_init:
	56	mflr r0
	57	/********************************************************************
	58	* Prefetch entire ext_bus_cntrl_init function into the icache.
	59	* This is necessary because we are going to change the same CS we
	60	* are executing from. Otherwise a CPU lockup may occur.
	61	*******************************************************************/
	62	bl ..getAddr
	63	..getAddr:
	64	mflr r3 /* get address of ..getAddr */
	65
	66	/* Calculate number of cache lines for this function */
6d0f6bcf	67	addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
cd0a9de6 WD	68	mtctr r4
	69	..ebcloop:
	70	icbt r0, r3 /* prefetch cache line for addr in r3*/
6d0f6bcf	71	addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
cd0a9de6 WD	72	bdnz ..ebcloop /* continue for $CTR cache lines */
	73
	74	/********************************************************************
	75	* Delay to ensure all accesses to ROM are complete before changing
	76	* bank 0 timings. 200usec should be enough.
	77	* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
	78	*******************************************************************/
	79	addis r3, 0, 0x0
	80	ori r3, r3, 0xA000 /* wait 200us from reset */
	81	mtctr r3
	82	..spinlp:
	83	bdnz ..spinlp /* spin loop */
	84
	85	/********************************************************************
	86	* SETUP CPC0_CR0
	87	*******************************************************************/
	88	LI32(r4, 0x007000c0)
d1c3b275	89	mtdcr CPC0_CR0, r4
cd0a9de6 WD	90
	91	/********************************************************************
	92	* Setup CPC0_CR1: Change PCIINT signal to PerWE
	93	*******************************************************************/
d1c3b275	94	mfdcr r4, CPC0_CR1
cd0a9de6	95	ori r4, r4, 0x4000
d1c3b275	96	mtdcr CPC0_CR1, r4
cd0a9de6 WD	97
	98	/********************************************************************
	99	* Setup External Bus Controller (EBC).
	100	*******************************************************************/
d1c3b275	101	WDCR_EBC(EBC0_CFG, 0xd84c0000)
cd0a9de6 WD	102	/********************************************************************
	103	* Memory Bank 0 (Intel 28F128J3 Flash) initialization
	104	*******************************************************************/
d1c3b275 SR	105	/WDCR_EBC(PB1AP, 0x02869200)/
	106	WDCR_EBC(PB1AP, 0x07869200)
	107	WDCR_EBC(PB0CR, 0xfe0bc000)
cd0a9de6 WD	108	/********************************************************************
	109	* Memory Bank 1 (Holtek HT6542B PS/2) initialization
	110	*******************************************************************/
d1c3b275 SR	111	WDCR_EBC(PB1AP, 0x1f869200)
d1c3b275 SR	112	WDCR_EBC(PB1CR, 0xf0818000)
cd0a9de6 WD	113	/********************************************************************
	114	* Memory Bank 2 (Epson S1D13506) initialization
	115	*******************************************************************/
d1c3b275 SR	116	WDCR_EBC(PB2AP, 0x05860300)
d1c3b275 SR	117	WDCR_EBC(PB2CR, 0xf045a000)
cd0a9de6 WD	118	/********************************************************************
	119	* Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
	120	*******************************************************************/
d1c3b275 SR	121	WDCR_EBC(PB3AP, 0x0387d200)
d1c3b275 SR	122	WDCR_EBC(PB3CR, 0xf021c000)
cd0a9de6 WD	123	/********************************************************************
	124	* Memory Bank 4-7 (Unused) initialization
	125	*******************************************************************/
d1c3b275 SR	126	WDCR_EBC(PB4AP, 0)
	127	WDCR_EBC(PB4CR, 0)
	128	WDCR_EBC(PB5AP, 0)
	129	WDCR_EBC(PB5CR, 0)
	130	WDCR_EBC(PB6AP, 0)
	131	WDCR_EBC(PB6CR, 0)
	132	WDCR_EBC(PB7AP, 0)
	133	WDCR_EBC(PB7CR, 0)
cd0a9de6 WD	134
	135	/* We are all done */
	136	mtlr r0 /* Restore link register */
	137	blr /* Return to calling function */
	138	.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
	139	/* end ext_bus_cntlr_init() */
	140
	141	/******************************************************************************
	142	* Function: sdram_init
	143	*
	144	* Description: Configures SDRAM memory banks.
	145	*
	146	* Notes: Does NOT use the stack.
	147	*****************************************************************************/
	148	.section ".text"
	149	.align 2
	150	.globl sdram_init
	151	.type sdram_init, @function
	152	sdram_init:
	153
	154	/*
	155	* Disable memory controller to allow
	156	* values to be changed.
	157	*/
95b602ba	158	WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
cd0a9de6 WD	159
	160	/*
	161	* Configure Memory Banks
	162	*/
95b602ba SR	163	WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
	164	WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
	165	WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
	166	WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
cd0a9de6 WD	167
	168	/*
	169	* Set up SDTR1 (SDRAM Timing Register)
	170	*/
95b602ba	171	WDCR_SDRAM(SDRAM0_TR, 0x00854009)
cd0a9de6 WD	172
	173	/*
	174	* Set RTR (Refresh Timing Register)
	175	*/
95b602ba SR	176	WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
95b602ba SR	177	/* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
cd0a9de6 WD	178
	179	/********************************************************************
	180	* Delay to ensure 200usec have elapsed since reset. Assume worst
	181	* case that the core is running 200Mhz:
	182	* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
	183	*******************************************************************/
	184	addis r3, 0, 0x0000
	185	ori r3, r3, 0xA000 /* Wait >200us from reset */
	186	mtctr r3
	187	..spinlp2:
	188	bdnz ..spinlp2 /* spin loop */
	189
	190	/********************************************************************
	191	* Set memory controller options reg, MCOPT1.
	192	*******************************************************************/
95b602ba	193	WDCR_SDRAM(SDRAM0_CFG,0x80800000)
cd0a9de6 WD	194
	195	..sdri_done:
	196	blr /* Return to calling function */
	197	.Lfe1: .size sdram_init,.Lfe1-sdram_init
	198	/* end sdram_init() */