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bfacf466 S |
1 | # |
2 | # Copyright (C) 2011 | |
3 | # Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net> | |
4 | # | |
5 | # Based on Kirkwood support: | |
6 | # (C) Copyright 2009 | |
7 | # Marvell Semiconductor <www.marvell.com> | |
8 | # Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
9 | # | |
1a459660 | 10 | # SPDX-License-Identifier: GPL-2.0+ |
bfacf466 | 11 | # |
b1e6c4c3 | 12 | # Refer doc/README.kwbimage for more details about how-to configure |
bfacf466 S |
13 | # and create kirkwood boot image |
14 | # | |
15 | ||
16 | # Boot Media configurations | |
17 | BOOT_FROM nand | |
18 | NAND_ECC_MODE default | |
19 | NAND_PAGE_SIZE 0x0800 | |
20 | ||
21 | # SOC registers configuration using bootrom header extension | |
22 | # Maximum KWBIMAGE_MAX_CONFIG configurations allowed | |
23 | ||
24 | # Configure RGMII-0 interface pad voltage to 1.8V | |
25 | DATA 0xFFD100e0 0x1b1b1b9b | |
26 | ||
27 | #Dram initalization for SINGLE x16 CL=5 @ 400MHz | |
28 | DATA 0xFFD01400 0x43000c30 # DDR Configuration register | |
29 | # bit13-0: 0xc30, 3120 DDR2 clks refresh rate | |
30 | # bit23-14: 0 required | |
31 | # bit24: 1, enable exit self refresh mode on DDR access | |
32 | # bit25: 1 required | |
33 | # bit29-26: 0 required | |
34 | # bit31-30: 0b01 required | |
35 | ||
36 | DATA 0xFFD01404 0x39543000 # DDR Controller Control Low | |
37 | # bit3-0: 0 required | |
38 | # bit4: 0, addr/cmd in smame cycle | |
39 | # bit5: 0, clk is driven during self refresh, we don't care for APX | |
40 | # bit6: 0, use recommended falling edge of clk for addr/cmd | |
41 | # bit11-7: 0 required | |
42 | # bit12: 1 required | |
43 | # bit13: 1 required | |
44 | # bit14: 0, input buffer always powered up | |
45 | # bit17-15: 0 required | |
46 | # bit18: 1, cpu lock transaction enabled | |
47 | # bit19: 0 required | |
48 | # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 | |
49 | # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM | |
50 | # bit30-28: 3 required | |
51 | # bit31: 0, no additional STARTBURST delay | |
52 | ||
53 | DATA 0xFFD01408 0x22125451 # DDR Timing (Low) | |
54 | # bit3-0: 1, 18 cycle tRAS (tRAS[3-0]) | |
55 | # bit7-4: 5, 6 cycle tRCD | |
56 | # bit11-8: 4, 5 cyle tRP | |
57 | # bit15-12: 5, 6 cyle tWR | |
58 | # bit19-16: 2, 3 cyle tWTR | |
59 | # bit20: 1, 18 cycle tRAS (tRAS[4]) | |
60 | # bit23-21: 0 required | |
61 | # bit27-24: 2, 3 cycle tRRD | |
62 | # bit31-28: 2, 3 cyle tRTP | |
63 | ||
64 | DATA 0xFFD0140C 0x00000833 # DDR Timing (High) | |
65 | # bit6-0: 0x33, 33 cycle tRFC | |
66 | # bit8-7: 0, 1 cycle tR2R | |
67 | # bit10-9: 0, 1 cyle tR2W | |
68 | # bit12-11: 1, 2 cylce tW2W | |
69 | # bit31-13: 0 required | |
70 | ||
71 | DATA 0xFFD01410 0x0000000c # DDR Address Control | |
72 | # bit1-0: 0, Cs0width=x8 | |
73 | # bit3-2: 3, Cs0size=1Gb | |
74 | # bit5-4: 0, Cs1width=nonexistent | |
75 | # bit7-6: 0, Cs1size=nonexistent | |
76 | # bit9-8: 0, Cs2width=nonexistent | |
77 | # bit11-10: 0, Cs2size=nonexistent | |
78 | # bit13-12: 0, Cs3width=nonexistent | |
79 | # bit15-14: 0, Cs3size=nonexistent | |
80 | # bit16: 0, Cs0AddrSel | |
81 | # bit17: 0, Cs1AddrSel | |
82 | # bit18: 0, Cs2AddrSel | |
83 | # bit19: 0, Cs3AddrSel | |
84 | # bit31-20: 0 required | |
85 | ||
86 | DATA 0xFFD01414 0x00000000 # DDR Open Pages Control | |
87 | # bit0: 0, OPEn=OpenPage enabled | |
88 | # bit31-1: 0 required | |
89 | ||
90 | DATA 0xFFD01418 0x00000000 # DDR Operation | |
91 | # bit3-0: 0, Cmd=Normal SDRAM Mode | |
92 | # bit31-4: 0 required | |
93 | ||
94 | DATA 0xFFD0141C 0x00000C52 # DDR Mode | |
95 | # bit2-0: 2, Burst Length (2 required) | |
96 | # bit3: 0, Burst Type (0 required) | |
97 | # bit6-4: 5, CAS Latency (CL) 5 | |
98 | # bit7: 0, (Test Mode) Normal operation | |
99 | # bit8: 0, (Reset DLL) Normal operation | |
100 | # bit11-9: 0, Write recovery for auto-precharge (3 required ??) | |
101 | # bit12: 0, Fast Active power down exit time (0 required) | |
102 | # bit31-13: 0 required | |
103 | ||
104 | DATA 0xFFD01420 0x00000040 # DDR Extended Mode | |
105 | # bit0: 0, DRAM DLL enabled | |
106 | # bit1: 0, DRAM drive strength normal | |
107 | # bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination) | |
108 | # bit5-3: 0 required | |
109 | # bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination) | |
110 | # bit9-7: 0 required | |
111 | # bit10: 0, differential DQS enabled | |
112 | # bit11: 0 required | |
113 | # bit12: 0, DRAM output buffer enabled | |
114 | # bit31-13: 0 required | |
115 | ||
116 | DATA 0xFFD01424 0x0000F17F # DDR Controller Control High | |
117 | # bit2-0: 0x7 required | |
118 | # bit3: 1, MBUS Burst Chop disabled | |
119 | # bit6-4: 0x7 required | |
120 | # bit7: 0 required | |
121 | # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz | |
122 | # bit9: 0, no half clock cycle addition to dataout | |
123 | # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals | |
124 | # bit11: 0, 1/4 clock cycle skew disabled for write mesh | |
125 | # bit15-12: 0xf required | |
126 | # bit31-16: 0 required | |
127 | ||
128 | DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing | |
129 | # bit3-0: 0 required | |
130 | # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal | |
131 | # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal | |
132 | # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal | |
133 | # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal | |
134 | # bit31-20: 0 required | |
135 | ||
136 | DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing | |
137 | # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal | |
138 | # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal | |
139 | # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal | |
140 | # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal | |
141 | # bit31-16: 0 required | |
142 | ||
143 | DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 | |
144 | DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size | |
145 | # bit0: 1, Window enabled | |
146 | # bit1: 0, Write Protect disabled | |
147 | # bit3-2: 0x0, CS0 hit selected | |
148 | # bit23-4: 0xfffff required | |
149 | # bit31-24: 0x0f, Size (i.e. 256MB) | |
150 | ||
151 | DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb | |
152 | DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 | |
153 | # bit0: 1, Window enabled | |
154 | # bit1: 0, Write Protect disabled | |
155 | # bit3-2: 1, CS1 hit selected | |
156 | # bit23-4: 0xfffff required | |
157 | # bit31-24: 0x0f, Size (i.e. 256MB) | |
158 | ||
159 | DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled | |
160 | DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled | |
161 | ||
162 | DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) | |
163 | # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM | |
164 | # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM | |
165 | # bit15-8: 0 required | |
166 | # bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1 | |
167 | # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM | |
168 | # bit31-24: 0 required | |
169 | ||
170 | DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) | |
171 | # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register | |
172 | # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register | |
173 | # bit31-4 0 required | |
174 | ||
175 | DATA 0xFFD0149C 0x0000E803 # CPU ODT Control | |
176 | # bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1 | |
177 | # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4 | |
178 | # bit9-8: 0, Internal ODT assertion is controlled by fiels | |
179 | # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm | |
180 | # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm | |
181 | # bit14: 1, M_STARTBURST_IN ODT enabled | |
182 | # bit15: 1, DDR IO ODT Unit: Drive ODT calibration values | |
183 | # bit20-16: 0, Pad N channel driving strength for ODT | |
184 | # bit25-21: 0, Pad P channel driving strength for ODT | |
185 | # bit31-26: 0 required | |
186 | ||
187 | DATA 0xFFD01480 0x00000001 # DDR Initialization Control | |
188 | # bit0: 1, enable DDR init upon this register write | |
189 | # bit31-1: 0, required | |
190 | ||
191 | # End of Header extension | |
192 | DATA 0x0 0x0 |