[thirdparty/u-boot.git] / board / dave / PPChameleonEVB / PPChameleonEVB.c

/*
 * (C) Copyright 2003
 * DAVE Srl
 * http://www.dave-tech.it
 * http://www.wawnet.biz
 * mailto:info@wawnet.biz
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */

int board_early_init_f (void)
{
	out32(GPIO0_OR, CONFIG_SYS_NAND0_CE);                 /* set initial outputs     */
	out32(GPIO0_OR, CONFIG_SYS_NAND1_CE);                 /* set initial outputs     */

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0)
	 * IRQ 26 (EXT IRQ 1)
	 * IRQ 27 (EXT IRQ 2)
	 * IRQ 28 (EXT IRQ 3)
	 * IRQ 29 (EXT IRQ 4)
	 * IRQ 30 (EXT IRQ 5)
	 * IRQ 31 (EXT IRQ 6)
	 */
	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */

	/*
	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	 */
#if 1 /* test-only */
	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
#else
	mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */
#endif
	return 0;
}

/* ------------------------------------------------------------------------- */

int misc_init_f (void)
{
	return 0;  /* dummy implementation */
}

extern flash_info_t flash_info[];	/* info for FLASH chips */

int misc_init_r (void)
{
	/* adjust flash start and size as well as the offset */
	gd->bd->bi_flashstart = 0 - flash_info[0].size;
	gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
#if 0
	volatile unsigned short *fpga_mode =
		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
	volatile unsigned char *duart0_mcr =
		(unsigned char *)((ulong)DUART0_BA + 4);
	volatile unsigned char *duart1_mcr =
		(unsigned char *)((ulong)DUART1_BA + 4);

	bd_t *bd = gd->bd;
	char *	tmp;                    /* Temporary char pointer      */
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;
	unsigned long CPC0_CR0Reg;

	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
		printf ("GUNZIP ERROR - must RESET board to recover\n");
		do_reset (NULL, 0, 0, NULL);
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');
		/* delayed reboot */
		for (i=20; i>0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index=0;index<1000;index++)
				udelay(1000);
		}
		putc ('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index+1]));
		index += len+3;
	}
	putc ('\n');

	free(dst);

	/*
	 * Reset FPGA via FPGA_DATA pin
	 */
	SET_FPGA(FPGA_PRG | FPGA_CLK);
	udelay(1000); /* wait 1ms */
	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
	udelay(1000); /* wait 1ms */
#endif

#if 0
	/*
	 * Enable power on PS/2 interface
	 */
	*fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET;

	/*
	 * Enable interrupts in exar duart mcr[3]
	 */
	*duart0_mcr = 0x08;
	*duart1_mcr = 0x08;
#endif
	return (0);
}

/*
 * Check Board Identity:
 */

int checkboard (void)
{
	char str[64];
	int i = getenv_f("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming PPChameleonEVB");
	} else {
		puts(str);
	}

	putc ('\n');

	return 0;
}

/* ------------------------------------------------------------------------- */

int testdram (void)
{
	/* TODO: XXX XXX XXX */
	printf ("test: 16 MB - ok\n");

	return (0);
}

/* ------------------------------------------------------------------------- */

#ifdef CONFIG_CFB_CONSOLE
# ifdef CONFIG_CONSOLE_EXTRA_INFO
# include <video_fb.h>
extern GraphicDevice smi;

void video_get_info_str (int line_number, char *info)
{
	uint pvr = get_pvr ();

	/* init video info strings for graphic console */
	switch (line_number) {
	case 1:
		switch (pvr) {
		case PVR_405EP_RB:
			sprintf (info, " AMCC PowerPC 405EP Rev. B");
			break;
		default:
			sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
			break;
		}
		return;
	case 2:
		sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
		return;
	case 3:
		sprintf (info, " %s", smi.modeIdent);
		return;
	}

	/* no more info lines */
	*info = 0;
	return;
}
# endif	/* CONFIG_CONSOLE_EXTRA_INFO */
#endif	/* CONFIG_CFB_CONSOLE */
Commit	Line	Data
12f34241	1	/*
180d3f74 WD	2	* (C) Copyright 2003
	3	* DAVE Srl
	4	* http://www.dave-tech.it
	5	* http://www.wawnet.biz
	6	* mailto:info@wawnet.biz
12f34241	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
12f34241 WD	9	*/
	10
	11	#include <common.h>
	12	#include <asm/processor.h>
	13	#include <command.h>
	14	#include <malloc.h>
	15
d87080b7 WD	16	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	17
e55ca7e2	18	/* ------------------------------------------------------------------------- */
12f34241	19
c837dcb1	20	int board_early_init_f (void)
12f34241	21	{
6d0f6bcf JCPV	22	out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */
6d0f6bcf JCPV	23	out32(GPIO0_OR, CONFIG_SYS_NAND1_CE); /* set initial outputs */
12f34241 WD	24
	25	/*
	26	* IRQ 0-15 405GP internally generated; active high; level sensitive
	27	* IRQ 16 405GP internally generated; active low; level sensitive
	28	* IRQ 17-24 RESERVED
e55ca7e2 WD	29	* IRQ 25 (EXT IRQ 0)
	30	* IRQ 26 (EXT IRQ 1)
	31	* IRQ 27 (EXT IRQ 2)
	32	* IRQ 28 (EXT IRQ 3)
	33	* IRQ 29 (EXT IRQ 4)
	34	* IRQ 30 (EXT IRQ 5)
	35	* IRQ 31 (EXT IRQ 6)
12f34241	36	*/
952e7760 SR	37	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
	38	mtdcr(UIC0ER, 0x00000000); /* disable all ints */
	39	mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
	40	mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
	41	mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
	42	mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
	43	mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
12f34241 WD	44
	45	/*
	46	* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	47	*/
	48	#if 1 /* test-only */
d1c3b275	49	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
12f34241	50	#else
d1c3b275	51	mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */
12f34241	52	#endif
12f34241 WD	53	return 0;
	54	}
	55
12f34241 WD	56	/* ------------------------------------------------------------------------- */
	57
	58	int misc_init_f (void)
	59	{
	60	return 0; /* dummy implementation */
	61	}
	62
46a414dc	63	extern flash_info_t flash_info[]; /* info for FLASH chips */
12f34241 WD	64
	65	int misc_init_r (void)
	66	{
46a414dc WD	67	/* adjust flash start and size as well as the offset */
46a414dc WD	68	gd->bd->bi_flashstart = 0 - flash_info[0].size;
6d0f6bcf	69	gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
12f34241 WD	70	#if 0
12f34241 WD	71	volatile unsigned short *fpga_mode =
6d0f6bcf	72	(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
12f34241 WD	73	volatile unsigned char *duart0_mcr =
	74	(unsigned char *)((ulong)DUART0_BA + 4);
	75	volatile unsigned char *duart1_mcr =
	76	(unsigned char *)((ulong)DUART1_BA + 4);
	77
	78	bd_t *bd = gd->bd;
	79	char * tmp; /* Temporary char pointer */
	80	unsigned char *dst;
	81	ulong len = sizeof(fpgadata);
	82	int status;
	83	int index;
	84	int i;
d1c3b275	85	unsigned long CPC0_CR0Reg;
12f34241	86
6d0f6bcf JCPV	87	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
6d0f6bcf JCPV	88	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
12f34241 WD	89	printf ("GUNZIP ERROR - must RESET board to recover\n");
	90	do_reset (NULL, 0, 0, NULL);
	91	}
	92
	93	status = fpga_boot(dst, len);
	94	if (status != 0) {
	95	printf("\nFPGA: Booting failed ");
	96	switch (status) {
	97	case ERROR_FPGA_PRG_INIT_LOW:
	98	printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	99	break;
	100	case ERROR_FPGA_PRG_INIT_HIGH:
	101	printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	102	break;
	103	case ERROR_FPGA_PRG_DONE:
	104	printf("(Timeout: DONE not high after programming FPGA)\n ");
	105	break;
	106	}
	107
	108	/* display infos on fpgaimage */
	109	index = 15;
	110	for (i=0; i<4; i++) {
	111	len = dst[index];
	112	printf("FPGA: %s\n", &(dst[index+1]));
	113	index += len+3;
	114	}
	115	putc ('\n');
	116	/* delayed reboot */
	117	for (i=20; i>0; i--) {
	118	printf("Rebooting in %2d seconds \r",i);
	119	for (index=0;index<1000;index++)
	120	udelay(1000);
	121	}
	122	putc ('\n');
	123	do_reset(NULL, 0, 0, NULL);
	124	}
	125
	126	puts("FPGA: ");
	127
	128	/* display infos on fpgaimage */
	129	index = 15;
	130	for (i=0; i<4; i++) {
	131	len = dst[index];
	132	printf("%s ", &(dst[index+1]));
	133	index += len+3;
	134	}
	135	putc ('\n');
	136
	137	free(dst);
	138
	139	/*
	140	* Reset FPGA via FPGA_DATA pin
	141	*/
	142	SET_FPGA(FPGA_PRG \| FPGA_CLK);
	143	udelay(1000); /* wait 1ms */
	144	SET_FPGA(FPGA_PRG \| FPGA_CLK \| FPGA_DATA);
	145	udelay(1000); /* wait 1ms */
12f34241 WD	146	#endif
	147
	148	#if 0
	149	/*
	150	* Enable power on PS/2 interface
	151	*/
6d0f6bcf	152	*fpga_mode \|= CONFIG_SYS_FPGA_CTRL_PS2_RESET;
12f34241 WD	153
	154	/*
	155	* Enable interrupts in exar duart mcr[3]
	156	*/
	157	*duart0_mcr = 0x08;
	158	*duart1_mcr = 0x08;
	159	#endif
12f34241 WD	160	return (0);
	161	}
	162
12f34241 WD	163	/*
	164	* Check Board Identity:
	165	*/
	166
	167	int checkboard (void)
	168	{
77ddac94	169	char str[64];
cdb74977	170	int i = getenv_f("serial#", str, sizeof(str));
12f34241 WD	171
	172	puts ("Board: ");
	173
	174	if (i == -1) {
	175	puts ("### No HW ID - assuming PPChameleonEVB");
	176	} else {
	177	puts(str);
	178	}
	179
	180	putc ('\n');
	181
	182	return 0;
	183	}
	184
	185	/* ------------------------------------------------------------------------- */
	186
12f34241 WD	187	int testdram (void)
	188	{
	189	/* TODO: XXX XXX XXX */
	190	printf ("test: 16 MB - ok\n");
	191
	192	return (0);
	193	}
	194
	195	/* ------------------------------------------------------------------------- */
	196
e55ca7e2 WD	197	#ifdef CONFIG_CFB_CONSOLE
	198	# ifdef CONFIG_CONSOLE_EXTRA_INFO
	199	# include <video_fb.h>
	200	extern GraphicDevice smi;
	201
	202	void video_get_info_str (int line_number, char *info)
	203	{
	204	uint pvr = get_pvr ();
	205
	206	/* init video info strings for graphic console */
	207	switch (line_number) {
	208	case 1:
	209	switch (pvr) {
	210	case PVR_405EP_RB:
0c8721a4	211	sprintf (info, " AMCC PowerPC 405EP Rev. B");
e55ca7e2 WD	212	break;
e55ca7e2 WD	213	default:
0c8721a4	214	sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
e55ca7e2 WD	215	break;
	216	}
	217	return;
	218	case 2:
	219	sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
	220	return;
	221	case 3:
	222	sprintf (info, " %s", smi.modeIdent);
	223	return;
	224	}
	225
	226	/* no more info lines */
	227	*info = 0;
	228	return;
	229	}
	230	# endif /* CONFIG_CONSOLE_EXTRA_INFO */
	231	#endif /* CONFIG_CFB_CONSOLE */