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0d19f6c8 IY |
1 | /* |
2 | * | |
3 | * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
0d19f6c8 IY |
24 | #include <common.h> |
25 | #include <netdev.h> | |
26 | #include <asm/arch/mx31.h> | |
27 | #include <asm/arch/mx31-regs.h> | |
45997e0a | 28 | #include <nand.h> |
e98ecd71 | 29 | #include <fsl_pmic.h> |
c4ea1424 | 30 | #include <mxc_gpio.h> |
0d19f6c8 IY |
31 | #include "qong_fpga.h" |
32 | ||
33 | DECLARE_GLOBAL_DATA_PTR; | |
34 | ||
35 | int dram_init (void) | |
36 | { | |
e48b7c0a HS |
37 | /* dram_init must store complete ramsize in gd->ram_size */ |
38 | gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, | |
39 | PHYS_SDRAM_1_SIZE); | |
0d19f6c8 IY |
40 | return 0; |
41 | } | |
42 | ||
45997e0a SB |
43 | static void qong_fpga_reset(void) |
44 | { | |
c4ea1424 | 45 | mxc_gpio_set(QONG_FPGA_RST_PIN, 0); |
45997e0a | 46 | udelay(30); |
c4ea1424 | 47 | mxc_gpio_set(QONG_FPGA_RST_PIN, 1); |
45997e0a SB |
48 | |
49 | udelay(300); | |
50 | } | |
51 | ||
e48b7c0a HS |
52 | int board_early_init_f (void) |
53 | { | |
54 | #ifdef CONFIG_QONG_FPGA | |
55 | /* CS1: FPGA/Network Controller/GPIO */ | |
56 | /* 16-bit, no DTACK */ | |
57 | __REG(CSCR_U(1)) = 0x00000A01; | |
58 | __REG(CSCR_L(1)) = 0x20040501; | |
59 | __REG(CSCR_A(1)) = 0x04020C00; | |
60 | ||
61 | /* setup pins for FPGA */ | |
62 | mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); | |
63 | mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO)); | |
64 | mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO)); | |
65 | mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO)); | |
66 | mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO)); | |
67 | ||
68 | /* FPGA reset Pin */ | |
69 | /* rstn = 0 */ | |
c4ea1424 SB |
70 | mxc_gpio_set(QONG_FPGA_RST_PIN, 0); |
71 | mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT); | |
e48b7c0a HS |
72 | |
73 | /* set interrupt pin as input */ | |
c4ea1424 | 74 | mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN); |
e48b7c0a HS |
75 | |
76 | #endif | |
77 | ||
78 | /* setup pins for UART1 */ | |
79 | mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); | |
80 | mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); | |
81 | mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); | |
82 | mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); | |
83 | ||
84 | /* setup pins for SPI (pmic) */ | |
85 | mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); | |
86 | mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); | |
87 | mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); | |
88 | mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); | |
89 | mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); | |
90 | ||
91 | return 0; | |
92 | ||
93 | } | |
94 | ||
0d19f6c8 IY |
95 | int board_init (void) |
96 | { | |
97 | /* Chip selects */ | |
98 | /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */ | |
99 | /* Assumptions: HCLK = 133 MHz, tACC = 130ns */ | |
100 | __REG(CSCR_U(0)) = ((0 << 31) | /* SP */ | |
101 | (0 << 30) | /* WP */ | |
102 | (0 << 28) | /* BCD */ | |
103 | (0 << 24) | /* BCS */ | |
104 | (0 << 22) | /* PSZ */ | |
105 | (0 << 21) | /* PME */ | |
106 | (0 << 20) | /* SYNC */ | |
107 | (0 << 16) | /* DOL */ | |
108 | (3 << 14) | /* CNC */ | |
109 | (21 << 8) | /* WSC */ | |
110 | (0 << 7) | /* EW */ | |
111 | (0 << 4) | /* WWS */ | |
112 | (6 << 0) /* EDC */ | |
113 | ); | |
114 | ||
115 | __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */ | |
116 | (1 << 24) | /* OEN */ | |
117 | (3 << 20) | /* EBWA */ | |
118 | (3 << 16) | /* EBWN */ | |
119 | (1 << 12) | /* CSA */ | |
120 | (1 << 11) | /* EBC */ | |
121 | (5 << 8) | /* DSZ */ | |
122 | (1 << 4) | /* CSN */ | |
123 | (0 << 3) | /* PSR */ | |
124 | (0 << 2) | /* CRE */ | |
125 | (0 << 1) | /* WRAP */ | |
126 | (1 << 0) /* CSEN */ | |
127 | ); | |
128 | ||
129 | __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */ | |
130 | (1 << 24) | /* EBRN */ | |
131 | (2 << 20) | /* RWA */ | |
132 | (2 << 16) | /* RWN */ | |
133 | (0 << 15) | /* MUM */ | |
134 | (0 << 13) | /* LAH */ | |
135 | (2 << 10) | /* LBN */ | |
136 | (0 << 8) | /* LBA */ | |
137 | (0 << 6) | /* DWW */ | |
138 | (0 << 4) | /* DCT */ | |
139 | (0 << 3) | /* WWU */ | |
140 | (0 << 2) | /* AGE */ | |
141 | (0 << 1) | /* CNC2 */ | |
142 | (0 << 0) /* FCE */ | |
143 | ); | |
144 | ||
0d19f6c8 IY |
145 | /* board id for linux */ |
146 | gd->bd->bi_arch_number = MACH_TYPE_QONG; | |
147 | gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ | |
148 | ||
149 | return 0; | |
150 | } | |
151 | ||
e98ecd71 SB |
152 | int board_late_init(void) |
153 | { | |
154 | u32 val; | |
155 | ||
156 | /* Enable RTC battery */ | |
157 | val = pmic_reg_read(REG_POWER_CTL0); | |
158 | pmic_reg_write(REG_POWER_CTL0, val | COINCHEN); | |
159 | pmic_reg_write(REG_INT_STATUS1, RTCRSTI); | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
0d19f6c8 IY |
164 | int checkboard (void) |
165 | { | |
eeb50ce1 | 166 | printf("Board: DAVE/DENX Qong\n"); |
0d19f6c8 IY |
167 | return 0; |
168 | } | |
169 | ||
170 | int misc_init_r (void) | |
171 | { | |
172 | #ifdef CONFIG_QONG_FPGA | |
173 | u32 tmp; | |
174 | ||
0d19f6c8 IY |
175 | tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION; |
176 | printf("FPGA: "); | |
177 | printf("version register = %u.%u.%u\n", | |
178 | (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF); | |
179 | #endif | |
0d19f6c8 IY |
180 | return 0; |
181 | } | |
182 | ||
183 | int board_eth_init(bd_t *bis) | |
184 | { | |
185 | #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET) | |
186 | return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1); | |
187 | #else | |
188 | return 0; | |
189 | #endif | |
190 | } | |
45997e0a SB |
191 | |
192 | #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT) | |
193 | static void board_nand_setup(void) | |
194 | { | |
195 | ||
196 | /* CS3: NAND 8-bit */ | |
197 | __REG(CSCR_U(3)) = 0x00004f00; | |
198 | __REG(CSCR_L(3)) = 0x20013b31; | |
199 | __REG(CSCR_A(3)) = 0x00020800; | |
200 | __REG(IOMUXC_GPR) |= 1 << 13; | |
201 | ||
202 | mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); | |
203 | mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO)); | |
204 | mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO)); | |
205 | ||
206 | /* Make sure to reset the fpga else you cannot access NAND */ | |
207 | qong_fpga_reset(); | |
208 | ||
209 | /* Enable NAND flash */ | |
c4ea1424 SB |
210 | mxc_gpio_set(15, 1); |
211 | mxc_gpio_set(14, 1); | |
212 | mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT); | |
213 | mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN); | |
214 | mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN); | |
215 | mxc_gpio_set(15, 0); | |
45997e0a SB |
216 | |
217 | } | |
218 | ||
219 | int qong_nand_rdy(void *chip) | |
220 | { | |
221 | udelay(1); | |
c4ea1424 | 222 | return mxc_gpio_get(16); |
45997e0a SB |
223 | } |
224 | ||
225 | void qong_nand_select_chip(struct mtd_info *mtd, int chip) | |
226 | { | |
227 | if (chip >= 0) | |
c4ea1424 | 228 | mxc_gpio_set(15, 0); |
45997e0a | 229 | else |
c4ea1424 | 230 | mxc_gpio_set(15, 1); |
45997e0a SB |
231 | |
232 | } | |
233 | ||
234 | void qong_nand_plat_init(void *chip) | |
235 | { | |
236 | struct nand_chip *nand = (struct nand_chip *)chip; | |
237 | nand->chip_delay = 20; | |
238 | nand->select_chip = qong_nand_select_chip; | |
239 | nand->options &= ~NAND_BUSWIDTH_16; | |
240 | board_nand_setup(); | |
241 | } | |
242 | ||
243 | #endif |