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0d19f6c8 IY |
1 | /* |
2 | * | |
3 | * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
0d19f6c8 IY |
24 | #include <common.h> |
25 | #include <netdev.h> | |
26 | #include <asm/arch/mx31.h> | |
27 | #include <asm/arch/mx31-regs.h> | |
45997e0a | 28 | #include <nand.h> |
0d19f6c8 IY |
29 | #include "qong_fpga.h" |
30 | ||
31 | DECLARE_GLOBAL_DATA_PTR; | |
32 | ||
33 | int dram_init (void) | |
34 | { | |
35 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
36 | gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1, | |
37 | PHYS_SDRAM_1_SIZE); | |
38 | ||
39 | return 0; | |
40 | } | |
41 | ||
45997e0a SB |
42 | static void qong_fpga_reset(void) |
43 | { | |
44 | mx31_gpio_set(QONG_FPGA_RST_PIN, 0); | |
45 | udelay(30); | |
46 | mx31_gpio_set(QONG_FPGA_RST_PIN, 1); | |
47 | ||
48 | udelay(300); | |
49 | } | |
50 | ||
0d19f6c8 IY |
51 | int board_init (void) |
52 | { | |
53 | /* Chip selects */ | |
54 | /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */ | |
55 | /* Assumptions: HCLK = 133 MHz, tACC = 130ns */ | |
56 | __REG(CSCR_U(0)) = ((0 << 31) | /* SP */ | |
57 | (0 << 30) | /* WP */ | |
58 | (0 << 28) | /* BCD */ | |
59 | (0 << 24) | /* BCS */ | |
60 | (0 << 22) | /* PSZ */ | |
61 | (0 << 21) | /* PME */ | |
62 | (0 << 20) | /* SYNC */ | |
63 | (0 << 16) | /* DOL */ | |
64 | (3 << 14) | /* CNC */ | |
65 | (21 << 8) | /* WSC */ | |
66 | (0 << 7) | /* EW */ | |
67 | (0 << 4) | /* WWS */ | |
68 | (6 << 0) /* EDC */ | |
69 | ); | |
70 | ||
71 | __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */ | |
72 | (1 << 24) | /* OEN */ | |
73 | (3 << 20) | /* EBWA */ | |
74 | (3 << 16) | /* EBWN */ | |
75 | (1 << 12) | /* CSA */ | |
76 | (1 << 11) | /* EBC */ | |
77 | (5 << 8) | /* DSZ */ | |
78 | (1 << 4) | /* CSN */ | |
79 | (0 << 3) | /* PSR */ | |
80 | (0 << 2) | /* CRE */ | |
81 | (0 << 1) | /* WRAP */ | |
82 | (1 << 0) /* CSEN */ | |
83 | ); | |
84 | ||
85 | __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */ | |
86 | (1 << 24) | /* EBRN */ | |
87 | (2 << 20) | /* RWA */ | |
88 | (2 << 16) | /* RWN */ | |
89 | (0 << 15) | /* MUM */ | |
90 | (0 << 13) | /* LAH */ | |
91 | (2 << 10) | /* LBN */ | |
92 | (0 << 8) | /* LBA */ | |
93 | (0 << 6) | /* DWW */ | |
94 | (0 << 4) | /* DCT */ | |
95 | (0 << 3) | /* WWU */ | |
96 | (0 << 2) | /* AGE */ | |
97 | (0 << 1) | /* CNC2 */ | |
98 | (0 << 0) /* FCE */ | |
99 | ); | |
100 | ||
101 | #ifdef CONFIG_QONG_FPGA | |
102 | /* CS1: FPGA/Network Controller/GPIO */ | |
103 | /* 16-bit, no DTACK */ | |
104 | __REG(CSCR_U(1)) = 0x00000A01; | |
105 | __REG(CSCR_L(1)) = 0x20040501; | |
106 | __REG(CSCR_A(1)) = 0x04020C00; | |
107 | ||
108 | /* setup pins for FPGA */ | |
109 | mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); | |
110 | mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO)); | |
111 | mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO)); | |
112 | mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO)); | |
113 | mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO)); | |
45997e0a SB |
114 | |
115 | /* FPGA reset Pin */ | |
116 | /* rstn = 0 */ | |
117 | mx31_gpio_set(QONG_FPGA_RST_PIN, 0); | |
118 | mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT); | |
119 | ||
120 | /* set interrupt pin as input */ | |
121 | mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN); | |
122 | ||
0d19f6c8 IY |
123 | #endif |
124 | ||
125 | /* setup pins for UART1 */ | |
126 | mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); | |
127 | mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); | |
128 | mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); | |
129 | mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); | |
130 | ||
131 | /* board id for linux */ | |
132 | gd->bd->bi_arch_number = MACH_TYPE_QONG; | |
133 | gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
138 | int checkboard (void) | |
139 | { | |
eeb50ce1 | 140 | printf("Board: DAVE/DENX Qong\n"); |
0d19f6c8 IY |
141 | return 0; |
142 | } | |
143 | ||
144 | int misc_init_r (void) | |
145 | { | |
146 | #ifdef CONFIG_QONG_FPGA | |
147 | u32 tmp; | |
148 | ||
0d19f6c8 IY |
149 | tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION; |
150 | printf("FPGA: "); | |
151 | printf("version register = %u.%u.%u\n", | |
152 | (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF); | |
153 | #endif | |
0d19f6c8 IY |
154 | return 0; |
155 | } | |
156 | ||
157 | int board_eth_init(bd_t *bis) | |
158 | { | |
159 | #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET) | |
160 | return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1); | |
161 | #else | |
162 | return 0; | |
163 | #endif | |
164 | } | |
45997e0a SB |
165 | |
166 | #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT) | |
167 | static void board_nand_setup(void) | |
168 | { | |
169 | ||
170 | /* CS3: NAND 8-bit */ | |
171 | __REG(CSCR_U(3)) = 0x00004f00; | |
172 | __REG(CSCR_L(3)) = 0x20013b31; | |
173 | __REG(CSCR_A(3)) = 0x00020800; | |
174 | __REG(IOMUXC_GPR) |= 1 << 13; | |
175 | ||
176 | mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); | |
177 | mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO)); | |
178 | mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO)); | |
179 | ||
180 | /* Make sure to reset the fpga else you cannot access NAND */ | |
181 | qong_fpga_reset(); | |
182 | ||
183 | /* Enable NAND flash */ | |
184 | mx31_gpio_set(15, 1); | |
185 | mx31_gpio_set(14, 1); | |
186 | mx31_gpio_direction(15, MX31_GPIO_DIRECTION_OUT); | |
187 | mx31_gpio_direction(16, MX31_GPIO_DIRECTION_IN); | |
188 | mx31_gpio_direction(14, MX31_GPIO_DIRECTION_IN); | |
189 | mx31_gpio_set(15, 0); | |
190 | ||
191 | } | |
192 | ||
193 | int qong_nand_rdy(void *chip) | |
194 | { | |
195 | udelay(1); | |
196 | return mx31_gpio_get(16); | |
197 | } | |
198 | ||
199 | void qong_nand_select_chip(struct mtd_info *mtd, int chip) | |
200 | { | |
201 | if (chip >= 0) | |
202 | mx31_gpio_set(15, 0); | |
203 | else | |
204 | mx31_gpio_set(15, 1); | |
205 | ||
206 | } | |
207 | ||
208 | void qong_nand_plat_init(void *chip) | |
209 | { | |
210 | struct nand_chip *nand = (struct nand_chip *)chip; | |
211 | nand->chip_delay = 20; | |
212 | nand->select_chip = qong_nand_select_chip; | |
213 | nand->options &= ~NAND_BUSWIDTH_16; | |
214 | board_nand_setup(); | |
215 | } | |
216 | ||
217 | #endif |