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264bbdd1 HV |
1 | /* |
2 | * Power and Sleep Controller (PSC) functions. | |
3 | * | |
4 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
5 | * Copyright (C) 2008 Lyrtech <www.lyrtech.com> | |
6 | * Copyright (C) 2004 Texas Instruments. | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <asm/arch/hardware.h> | |
28 | ||
29 | /* | |
30 | * The DM6446 includes two separate power domains: "Always On" and "DSP". The | |
31 | * "Always On" power domain is always on when the chip is on. The "Always On" | |
32 | * domain is powered by the VDD pins of the DM6446. The majority of the | |
33 | * DM6446's modules lie within the "Always On" power domain. A separate | |
34 | * domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain | |
35 | * is not always on. The "DSP" power domain is powered by the CVDDDSP pins of | |
36 | * the DM6446. | |
37 | */ | |
38 | ||
39 | /* Works on Always On power domain only (no PD argument) */ | |
40 | void lpsc_on(unsigned int id) | |
41 | { | |
42 | dv_reg_p mdstat, mdctl; | |
43 | ||
44 | if (id >= DAVINCI_LPSC_GEM) | |
45 | return; /* Don't work on DSP Power Domain */ | |
46 | ||
47 | mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); | |
48 | mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); | |
49 | ||
50 | while (REG(PSC_PTSTAT) & 0x01); | |
51 | ||
52 | if ((*mdstat & 0x1f) == 0x03) | |
53 | return; /* Already on and enabled */ | |
54 | ||
55 | *mdctl |= 0x03; | |
56 | ||
57 | /* Special treatment for some modules as for sprue14 p.7.4.2 */ | |
58 | switch (id) { | |
59 | case DAVINCI_LPSC_VPSSSLV: | |
60 | case DAVINCI_LPSC_EMAC: | |
61 | case DAVINCI_LPSC_EMAC_WRAPPER: | |
62 | case DAVINCI_LPSC_MDIO: | |
63 | case DAVINCI_LPSC_USB: | |
64 | case DAVINCI_LPSC_ATA: | |
65 | case DAVINCI_LPSC_VLYNQ: | |
66 | case DAVINCI_LPSC_UHPI: | |
67 | case DAVINCI_LPSC_DDR_EMIF: | |
68 | case DAVINCI_LPSC_AEMIF: | |
69 | case DAVINCI_LPSC_MMC_SD: | |
70 | case DAVINCI_LPSC_MEMSTICK: | |
71 | case DAVINCI_LPSC_McBSP: | |
72 | case DAVINCI_LPSC_GPIO: | |
73 | *mdctl |= 0x200; | |
74 | break; | |
75 | } | |
76 | ||
77 | REG(PSC_PTCMD) = 0x01; | |
78 | ||
79 | while (REG(PSC_PTSTAT) & 0x03); | |
80 | while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ | |
81 | } | |
82 | ||
83 | /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */ | |
6d0f6bcf | 84 | #if !defined(CONFIG_SYS_USE_DSPLINK) |
264bbdd1 HV |
85 | void dsp_on(void) |
86 | { | |
87 | int i; | |
88 | ||
89 | if (REG(PSC_PDSTAT1) & 0x1f) | |
90 | return; /* Already on */ | |
91 | ||
92 | REG(PSC_GBLCTL) |= 0x01; | |
93 | REG(PSC_PDCTL1) |= 0x01; | |
94 | REG(PSC_PDCTL1) &= ~0x100; | |
95 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; | |
96 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; | |
97 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; | |
98 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; | |
99 | REG(PSC_PTCMD) = 0x02; | |
100 | ||
101 | for (i = 0; i < 100; i++) { | |
102 | if (REG(PSC_EPCPR) & 0x02) | |
103 | break; | |
104 | } | |
105 | ||
106 | REG(PSC_CHP_SHRTSW) = 0x01; | |
107 | REG(PSC_PDCTL1) |= 0x100; | |
108 | REG(PSC_EPCCR) = 0x02; | |
109 | ||
110 | for (i = 0; i < 100; i++) { | |
111 | if (!(REG(PSC_PTSTAT) & 0x02)) | |
112 | break; | |
113 | } | |
114 | ||
115 | REG(PSC_GBLCTL) &= ~0x1f; | |
116 | } | |
6d0f6bcf | 117 | #endif /* CONFIG_SYS_USE_DSPLINK */ |