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c7f879ec HV |
1 | /* |
2 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
3 | * | |
4 | * Parts are shamelessly stolen from various TI sources, original copyright | |
5 | * follows: | |
6 | * ----------------------------------------------------------------- | |
7 | * | |
8 | * Copyright (C) 2004 Texas Instruments. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * ---------------------------------------------------------------------------- | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <i2c.h> | |
29 | #include <asm/arch/hardware.h> | |
30 | #include <asm/arch/emac_defs.h> | |
31 | ||
32 | DECLARE_GLOBAL_DATA_PTR; | |
33 | ||
34 | extern void timer_init(void); | |
35 | extern int eth_hw_init(void); | |
36 | extern phy_t phy; | |
37 | ||
38 | ||
39 | /* Works on Always On power domain only (no PD argument) */ | |
40 | void lpsc_on(unsigned int id) | |
41 | { | |
42 | dv_reg_p mdstat, mdctl; | |
43 | ||
44 | if (id >= DAVINCI_LPSC_GEM) | |
45 | return; /* Don't work on DSP Power Domain */ | |
46 | ||
47 | mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); | |
48 | mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); | |
49 | ||
50 | while (REG(PSC_PTSTAT) & 0x01); | |
51 | ||
52 | if ((*mdstat & 0x1f) == 0x03) | |
53 | return; /* Already on and enabled */ | |
54 | ||
55 | *mdctl |= 0x03; | |
56 | ||
57 | /* Special treatment for some modules as for sprue14 p.7.4.2 */ | |
58 | if ((id == DAVINCI_LPSC_VPSSSLV) || | |
59 | (id == DAVINCI_LPSC_EMAC) || | |
60 | (id == DAVINCI_LPSC_EMAC_WRAPPER) || | |
61 | (id == DAVINCI_LPSC_MDIO) || | |
62 | (id == DAVINCI_LPSC_USB) || | |
63 | (id == DAVINCI_LPSC_ATA) || | |
64 | (id == DAVINCI_LPSC_VLYNQ) || | |
65 | (id == DAVINCI_LPSC_UHPI) || | |
66 | (id == DAVINCI_LPSC_DDR_EMIF) || | |
67 | (id == DAVINCI_LPSC_AEMIF) || | |
68 | (id == DAVINCI_LPSC_MMC_SD) || | |
69 | (id == DAVINCI_LPSC_MEMSTICK) || | |
70 | (id == DAVINCI_LPSC_McBSP) || | |
71 | (id == DAVINCI_LPSC_GPIO)) | |
72 | * mdctl |= 0x200; | |
73 | ||
74 | REG(PSC_PTCMD) = 0x01; | |
75 | ||
76 | while (REG(PSC_PTSTAT) & 0x03); | |
77 | while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ | |
78 | } | |
79 | ||
80 | void dsp_on(void) | |
81 | { | |
82 | int i; | |
83 | ||
84 | if (REG(PSC_PDSTAT1) & 0x1f) | |
85 | return; /* Already on */ | |
86 | ||
87 | REG(PSC_GBLCTL) |= 0x01; | |
88 | REG(PSC_PDCTL1) |= 0x01; | |
89 | REG(PSC_PDCTL1) &= ~0x100; | |
90 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; | |
91 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; | |
92 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; | |
93 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; | |
94 | REG(PSC_PTCMD) = 0x02; | |
95 | ||
96 | for (i = 0; i < 100; i++) { | |
97 | if (REG(PSC_EPCPR) & 0x02) | |
98 | break; | |
99 | } | |
100 | ||
101 | REG(PSC_CHP_SHRTSW) = 0x01; | |
102 | REG(PSC_PDCTL1) |= 0x100; | |
103 | REG(PSC_EPCCR) = 0x02; | |
104 | ||
105 | for (i = 0; i < 100; i++) { | |
106 | if (!(REG(PSC_PTSTAT) & 0x02)) | |
107 | break; | |
108 | } | |
109 | ||
110 | REG(PSC_GBLCTL) &= ~0x1f; | |
111 | } | |
112 | ||
113 | ||
114 | int board_init(void) | |
115 | { | |
116 | /* arch number of the board */ | |
117 | gd->bd->bi_arch_number = MACH_TYPE_SFFSDR; | |
118 | ||
119 | /* address of boot parameters */ | |
120 | gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; | |
121 | ||
122 | /* Workaround for TMS320DM6446 errata 1.3.22 */ | |
123 | REG(PSC_SILVER_BULLET) = 0; | |
124 | ||
125 | /* Power on required peripherals */ | |
126 | lpsc_on(DAVINCI_LPSC_EMAC); | |
127 | lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); | |
128 | lpsc_on(DAVINCI_LPSC_MDIO); | |
129 | lpsc_on(DAVINCI_LPSC_I2C); | |
130 | lpsc_on(DAVINCI_LPSC_UART0); | |
131 | lpsc_on(DAVINCI_LPSC_TIMER1); | |
132 | lpsc_on(DAVINCI_LPSC_GPIO); | |
133 | ||
134 | /* Powerup the DSP */ | |
135 | dsp_on(); | |
136 | ||
137 | /* Bringup UART0 out of reset */ | |
138 | REG(UART0_PWREMU_MGMT) = 0x0000e003; | |
139 | ||
140 | /* Enable GIO3.3V cells used for EMAC */ | |
141 | REG(VDD3P3V_PWDN) = 0; | |
142 | ||
143 | /* Enable UART0 MUX lines */ | |
144 | REG(PINMUX1) |= 1; | |
145 | ||
146 | /* Enable EMAC and AEMIF pins */ | |
147 | REG(PINMUX0) = 0x80000c1f; | |
148 | ||
149 | /* Enable I2C pin Mux */ | |
150 | REG(PINMUX1) |= (1 << 7); | |
151 | ||
152 | /* Set the Bus Priority Register to appropriate value */ | |
153 | REG(VBPR) = 0x20; | |
154 | ||
155 | timer_init(); | |
156 | ||
157 | return(0); | |
158 | } | |
159 | ||
160 | int misc_init_r(void) | |
161 | { | |
162 | u_int8_t tmp[20], buf[10]; | |
163 | int i = 0; | |
164 | int clk = 0; | |
165 | ||
166 | clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); | |
167 | ||
168 | printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2); | |
169 | printf("DDR Clock: %dMHz\n", (clk / 2)); | |
170 | ||
171 | /* Configure I2C switch (PCA9543) to enable channel 0. */ | |
172 | tmp[0] = CFG_I2C_PCA9543_ENABLE_CH0; | |
173 | if (i2c_write(CFG_I2C_PCA9543_ADDR, 0, | |
174 | CFG_I2C_PCA9543_ADDR_LEN, tmp, 1)) | |
175 | printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR); | |
176 | ||
177 | /* Set Ethernet MAC address from EEPROM. | |
178 | * We must read 8 bytes because data is stored in little-endian. */ | |
179 | if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x05A8, | |
180 | CFG_I2C_EEPROM_ADDR_LEN, buf, 8)) { | |
181 | printf("Read from EEPROM @ 0x%02x failed\n", | |
182 | CFG_I2C_EEPROM_ADDR); | |
183 | } else { | |
184 | tmp[0] = 0xff; | |
185 | for (i = 0; i < 6; i++) | |
186 | tmp[0] &= buf[i]; | |
187 | ||
188 | if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { | |
189 | sprintf((char *)&tmp[0], | |
190 | "%02x:%02x:%02x:%02x:%02x:%02x", | |
191 | buf[3], buf[2], buf[1], buf[0], | |
192 | buf[7], buf[6]); | |
193 | setenv("ethaddr", (char *)&tmp[0]); | |
194 | } | |
195 | } | |
196 | ||
197 | if (!eth_hw_init()) { | |
198 | printf("Ethernet init failed\n"); | |
199 | } else { | |
200 | printf("ETH PHY: %s\n", phy.name); | |
201 | } | |
202 | ||
203 | return(0); | |
204 | } | |
205 | ||
206 | int dram_init(void) | |
207 | { | |
208 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
209 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
210 | ||
211 | return(0); | |
212 | } |