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1 | /* |
2 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
3 | * | |
4 | * Copyright (C) 2008 Lyrtech <www.lyrtech.com> | |
5 | * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> | |
6 | * | |
7 | * Parts are shamelessly stolen from various TI sources, original copyright | |
8 | * follows: | |
9 | * | |
10 | * Copyright (C) 2004 Texas Instruments. | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
28 | */ | |
29 | ||
30 | #include <common.h> | |
31 | #include <i2c.h> | |
32 | #include <asm/arch/hardware.h> | |
33 | #include <asm/arch/emac_defs.h> | |
34 | ||
35 | #define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */ | |
36 | #define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */ | |
37 | ||
38 | #define INTEGRITY_SYSCFG_OFFSET 0x7E8 | |
39 | #define INTEGRITY_CHECKWORD_OFFSET 0x7F8 | |
40 | #define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF | |
41 | ||
42 | DECLARE_GLOBAL_DATA_PTR; | |
43 | ||
44 | extern void timer_init(void); | |
45 | extern int eth_hw_init(void); | |
46 | extern phy_t phy; | |
47 | ||
48 | ||
49 | /* Works on Always On power domain only (no PD argument) */ | |
50 | void lpsc_on(unsigned int id) | |
51 | { | |
52 | dv_reg_p mdstat, mdctl; | |
53 | ||
54 | if (id >= DAVINCI_LPSC_GEM) | |
55 | return; /* Don't work on DSP Power Domain */ | |
56 | ||
57 | mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); | |
58 | mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); | |
59 | ||
60 | while (REG(PSC_PTSTAT) & 0x01); | |
61 | ||
62 | if ((*mdstat & 0x1f) == 0x03) | |
63 | return; /* Already on and enabled */ | |
64 | ||
65 | *mdctl |= 0x03; | |
66 | ||
67 | /* Special treatment for some modules as for sprue14 p.7.4.2 */ | |
68 | switch (id) { | |
69 | case DAVINCI_LPSC_VPSSSLV: | |
70 | case DAVINCI_LPSC_EMAC: | |
71 | case DAVINCI_LPSC_EMAC_WRAPPER: | |
72 | case DAVINCI_LPSC_MDIO: | |
73 | case DAVINCI_LPSC_USB: | |
74 | case DAVINCI_LPSC_ATA: | |
75 | case DAVINCI_LPSC_VLYNQ: | |
76 | case DAVINCI_LPSC_UHPI: | |
77 | case DAVINCI_LPSC_DDR_EMIF: | |
78 | case DAVINCI_LPSC_AEMIF: | |
79 | case DAVINCI_LPSC_MMC_SD: | |
80 | case DAVINCI_LPSC_MEMSTICK: | |
81 | case DAVINCI_LPSC_McBSP: | |
82 | case DAVINCI_LPSC_GPIO: | |
83 | *mdctl |= 0x200; | |
84 | break; | |
85 | } | |
86 | ||
87 | REG(PSC_PTCMD) = 0x01; | |
88 | ||
89 | while (REG(PSC_PTSTAT) & 0x03); | |
90 | while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ | |
91 | } | |
92 | ||
93 | #if !defined(CFG_USE_DSPLINK) | |
94 | void dsp_on(void) | |
95 | { | |
96 | int i; | |
97 | ||
98 | if (REG(PSC_PDSTAT1) & 0x1f) | |
99 | return; /* Already on */ | |
100 | ||
101 | REG(PSC_GBLCTL) |= 0x01; | |
102 | REG(PSC_PDCTL1) |= 0x01; | |
103 | REG(PSC_PDCTL1) &= ~0x100; | |
104 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; | |
105 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; | |
106 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; | |
107 | REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; | |
108 | REG(PSC_PTCMD) = 0x02; | |
109 | ||
110 | for (i = 0; i < 100; i++) { | |
111 | if (REG(PSC_EPCPR) & 0x02) | |
112 | break; | |
113 | } | |
114 | ||
115 | REG(PSC_CHP_SHRTSW) = 0x01; | |
116 | REG(PSC_PDCTL1) |= 0x100; | |
117 | REG(PSC_EPCCR) = 0x02; | |
118 | ||
119 | for (i = 0; i < 100; i++) { | |
120 | if (!(REG(PSC_PTSTAT) & 0x02)) | |
121 | break; | |
122 | } | |
123 | ||
124 | REG(PSC_GBLCTL) &= ~0x1f; | |
125 | } | |
126 | #endif /* CFG_USE_DSPLINK */ | |
127 | ||
128 | int board_init(void) | |
129 | { | |
130 | /* arch number of the board */ | |
131 | gd->bd->bi_arch_number = MACH_TYPE_SFFSDR; | |
132 | ||
133 | /* address of boot parameters */ | |
134 | gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; | |
135 | ||
136 | /* Workaround for TMS320DM6446 errata 1.3.22 */ | |
137 | REG(PSC_SILVER_BULLET) = 0; | |
138 | ||
139 | /* Power on required peripherals */ | |
140 | lpsc_on(DAVINCI_LPSC_EMAC); | |
141 | lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); | |
142 | lpsc_on(DAVINCI_LPSC_MDIO); | |
143 | lpsc_on(DAVINCI_LPSC_I2C); | |
144 | lpsc_on(DAVINCI_LPSC_UART0); | |
145 | lpsc_on(DAVINCI_LPSC_TIMER1); | |
146 | lpsc_on(DAVINCI_LPSC_GPIO); | |
147 | ||
148 | #if !defined(CFG_USE_DSPLINK) | |
149 | /* Powerup the DSP */ | |
150 | dsp_on(); | |
151 | #endif /* CFG_USE_DSPLINK */ | |
152 | ||
153 | /* Bringup UART0 out of reset */ | |
154 | REG(UART0_PWREMU_MGMT) = 0x0000e003; | |
155 | ||
156 | /* Enable GIO3.3V cells used for EMAC */ | |
157 | REG(VDD3P3V_PWDN) = 0; | |
158 | ||
159 | /* Enable UART0 MUX lines */ | |
160 | REG(PINMUX1) |= 1; | |
161 | ||
162 | /* Enable EMAC and AEMIF pins */ | |
163 | REG(PINMUX0) = 0x80000c1f; | |
164 | ||
165 | /* Enable I2C pin Mux */ | |
166 | REG(PINMUX1) |= (1 << 7); | |
167 | ||
168 | /* Set the Bus Priority Register to appropriate value */ | |
169 | REG(VBPR) = 0x20; | |
170 | ||
171 | timer_init(); | |
172 | ||
173 | return(0); | |
174 | } | |
175 | ||
176 | /* Read ethernet MAC address from Integrity data structure inside EEPROM. */ | |
177 | int read_mac_address(uint8_t *buf) | |
178 | { | |
179 | u_int32_t value, mac[2], address; | |
180 | ||
181 | /* Read Integrity data structure checkword. */ | |
182 | if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET, | |
183 | CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) | |
184 | goto err; | |
185 | if (value != INTEGRITY_CHECKWORD_VALUE) | |
186 | return 1; | |
187 | ||
188 | /* Read SYSCFG structure offset. */ | |
189 | if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET, | |
190 | CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) | |
191 | goto err; | |
192 | address = 0x800 + (int) value; /* Address of SYSCFG structure. */ | |
193 | ||
194 | /* Read NET CONFIG structure offset. */ | |
195 | if (i2c_read(CFG_I2C_EEPROM_ADDR, address, | |
196 | CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) | |
197 | goto err; | |
198 | address = 0x800 + (int) value; /* Address of NET CONFIG structure. */ | |
199 | address += 12; /* Address of NET INTERFACE CONFIG structure. */ | |
200 | ||
201 | /* Read NET INTERFACE CONFIG 2 structure offset. */ | |
202 | if (i2c_read(CFG_I2C_EEPROM_ADDR, address, | |
203 | CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) | |
204 | goto err; | |
205 | address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE | |
206 | * CONFIG 2 structure. */ | |
207 | ||
208 | /* Read MAC address. */ | |
209 | if (i2c_read(CFG_I2C_EEPROM_ADDR, address, | |
210 | CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8)) | |
211 | goto err; | |
212 | ||
213 | buf[0] = mac[0] >> 24; | |
214 | buf[1] = mac[0] >> 16; | |
215 | buf[2] = mac[0] >> 8; | |
216 | buf[3] = mac[0]; | |
217 | buf[4] = mac[1] >> 24; | |
218 | buf[5] = mac[1] >> 16; | |
219 | ||
220 | return 0; | |
221 | ||
222 | err: | |
223 | printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR); | |
224 | return 1; | |
225 | } | |
226 | ||
227 | /* Platform dependent initialisation. */ | |
228 | int misc_init_r(void) | |
229 | { | |
230 | int i; | |
231 | u_int8_t i2cbuf; | |
232 | u_int8_t env_enetaddr[6], eeprom_enetaddr[6]; | |
233 | char *tmp = getenv("ethaddr"); | |
234 | char *end; | |
235 | int clk; | |
236 | ||
237 | /* EMIF-A CS3 configuration for FPGA. */ | |
238 | REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL; | |
239 | ||
240 | clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); | |
241 | ||
242 | printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2); | |
243 | printf("DDR Clock: %dMHz\n", (clk / 2)); | |
244 | ||
245 | /* Configure I2C switch (PCA9543) to enable channel 0. */ | |
246 | i2cbuf = CFG_I2C_PCA9543_ENABLE_CH0; | |
247 | if (i2c_write(CFG_I2C_PCA9543_ADDR, 0, | |
248 | CFG_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) { | |
249 | printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR); | |
250 | return 1; | |
251 | } | |
252 | ||
253 | /* Read Ethernet MAC address from the U-Boot environment. */ | |
254 | for (i = 0; i < 6; i++) { | |
255 | env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; | |
256 | if (tmp) | |
257 | tmp = (*end) ? end+1 : end; | |
258 | } | |
259 | ||
260 | /* Read Ethernet MAC address from EEPROM. */ | |
261 | if (read_mac_address(eeprom_enetaddr) == 0) { | |
262 | if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 && | |
263 | memcmp(env_enetaddr, eeprom_enetaddr, 6) != 0) { | |
264 | printf("\nWarning: MAC addresses don't match:\n"); | |
265 | printf("\tHW MAC address: " | |
266 | "%02X:%02X:%02X:%02X:%02X:%02X\n", | |
267 | eeprom_enetaddr[0], eeprom_enetaddr[1], | |
268 | eeprom_enetaddr[2], eeprom_enetaddr[3], | |
269 | eeprom_enetaddr[4], eeprom_enetaddr[5]); | |
270 | printf("\t\"ethaddr\" value: " | |
271 | "%02X:%02X:%02X:%02X:%02X:%02X\n", | |
272 | env_enetaddr[0], env_enetaddr[1], | |
273 | env_enetaddr[2], env_enetaddr[3], | |
274 | env_enetaddr[4], env_enetaddr[5]) ; | |
275 | debug("### Set MAC addr from environment\n"); | |
276 | memcpy(eeprom_enetaddr, env_enetaddr, 6); | |
277 | } | |
278 | if (!tmp) { | |
279 | char ethaddr[20]; | |
280 | ||
281 | sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", | |
282 | eeprom_enetaddr[0], eeprom_enetaddr[1], | |
283 | eeprom_enetaddr[2], eeprom_enetaddr[3], | |
284 | eeprom_enetaddr[4], eeprom_enetaddr[5]) ; | |
285 | debug("### Set environment from HW MAC addr = \"%s\"\n", | |
286 | ethaddr); | |
287 | setenv("ethaddr", ethaddr); | |
288 | } | |
289 | } | |
290 | ||
291 | if (!eth_hw_init()) { | |
292 | printf("Ethernet init failed\n"); | |
293 | } else { | |
294 | printf("ETH PHY: %s\n", phy.name); | |
295 | } | |
296 | ||
297 | /* On this platform, U-Boot is copied in RAM by the UBL, | |
298 | * so we are always in the relocated state. */ | |
299 | gd->flags |= GD_FLG_RELOC; | |
300 | ||
301 | return(0); | |
302 | } | |
303 | ||
304 | int dram_init(void) | |
305 | { | |
306 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
307 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
308 | ||
309 | return(0); | |
310 | } |