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2b1fa9d3 HV |
1 | /* |
2 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
3 | * | |
4 | * Copyright (C) 2008 Lyrtech <www.lyrtech.com> | |
5 | * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com> | |
6 | * | |
7 | * Parts are shamelessly stolen from various TI sources, original copyright | |
8 | * follows: | |
9 | * | |
10 | * Copyright (C) 2004 Texas Instruments. | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
28 | */ | |
29 | ||
30 | #include <common.h> | |
31 | #include <i2c.h> | |
32 | #include <asm/arch/hardware.h> | |
264bbdd1 | 33 | #include "../common/misc.h" |
2b1fa9d3 HV |
34 | |
35 | #define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */ | |
36 | #define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */ | |
37 | ||
38 | #define INTEGRITY_SYSCFG_OFFSET 0x7E8 | |
39 | #define INTEGRITY_CHECKWORD_OFFSET 0x7F8 | |
40 | #define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF | |
41 | ||
42 | DECLARE_GLOBAL_DATA_PTR; | |
43 | ||
2b1fa9d3 HV |
44 | int board_init(void) |
45 | { | |
46 | /* arch number of the board */ | |
47 | gd->bd->bi_arch_number = MACH_TYPE_SFFSDR; | |
48 | ||
49 | /* address of boot parameters */ | |
50 | gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; | |
51 | ||
0cd18fa9 | 52 | davinci_errata_workarounds(); |
2b1fa9d3 HV |
53 | |
54 | /* Power on required peripherals */ | |
2b1fa9d3 HV |
55 | lpsc_on(DAVINCI_LPSC_GPIO); |
56 | ||
6d0f6bcf | 57 | #if !defined(CONFIG_SYS_USE_DSPLINK) |
2b1fa9d3 HV |
58 | /* Powerup the DSP */ |
59 | dsp_on(); | |
6d0f6bcf | 60 | #endif /* CONFIG_SYS_USE_DSPLINK */ |
2b1fa9d3 | 61 | |
0cd18fa9 HV |
62 | davinci_enable_uart0(); |
63 | davinci_enable_emac(); | |
64 | davinci_enable_i2c(); | |
2b1fa9d3 | 65 | |
0cd18fa9 | 66 | lpsc_on(DAVINCI_LPSC_TIMER1); |
2b1fa9d3 HV |
67 | timer_init(); |
68 | ||
69 | return(0); | |
70 | } | |
71 | ||
264bbdd1 HV |
72 | /* Read ethernet MAC address from Integrity data structure inside EEPROM. |
73 | * Returns 1 if found, 0 otherwise. | |
74 | */ | |
75 | static int sffsdr_read_mac_address(uint8_t *buf) | |
2b1fa9d3 HV |
76 | { |
77 | u_int32_t value, mac[2], address; | |
78 | ||
79 | /* Read Integrity data structure checkword. */ | |
6d0f6bcf JCPV |
80 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET, |
81 | CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) | |
2b1fa9d3 HV |
82 | goto err; |
83 | if (value != INTEGRITY_CHECKWORD_VALUE) | |
264bbdd1 | 84 | return 0; |
2b1fa9d3 HV |
85 | |
86 | /* Read SYSCFG structure offset. */ | |
6d0f6bcf JCPV |
87 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET, |
88 | CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) | |
2b1fa9d3 HV |
89 | goto err; |
90 | address = 0x800 + (int) value; /* Address of SYSCFG structure. */ | |
91 | ||
92 | /* Read NET CONFIG structure offset. */ | |
6d0f6bcf JCPV |
93 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address, |
94 | CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) | |
2b1fa9d3 HV |
95 | goto err; |
96 | address = 0x800 + (int) value; /* Address of NET CONFIG structure. */ | |
97 | address += 12; /* Address of NET INTERFACE CONFIG structure. */ | |
98 | ||
99 | /* Read NET INTERFACE CONFIG 2 structure offset. */ | |
6d0f6bcf JCPV |
100 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address, |
101 | CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) | |
2b1fa9d3 HV |
102 | goto err; |
103 | address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE | |
104 | * CONFIG 2 structure. */ | |
105 | ||
106 | /* Read MAC address. */ | |
6d0f6bcf JCPV |
107 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address, |
108 | CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8)) | |
2b1fa9d3 HV |
109 | goto err; |
110 | ||
111 | buf[0] = mac[0] >> 24; | |
112 | buf[1] = mac[0] >> 16; | |
113 | buf[2] = mac[0] >> 8; | |
114 | buf[3] = mac[0]; | |
115 | buf[4] = mac[1] >> 24; | |
116 | buf[5] = mac[1] >> 16; | |
117 | ||
264bbdd1 | 118 | return 1; /* Found */ |
2b1fa9d3 HV |
119 | |
120 | err: | |
6d0f6bcf | 121 | printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR); |
264bbdd1 | 122 | return 0; |
2b1fa9d3 HV |
123 | } |
124 | ||
125 | /* Platform dependent initialisation. */ | |
126 | int misc_init_r(void) | |
127 | { | |
264bbdd1 HV |
128 | uint8_t i2cbuf; |
129 | uint8_t eeprom_enetaddr[6]; | |
2b1fa9d3 HV |
130 | |
131 | /* EMIF-A CS3 configuration for FPGA. */ | |
132 | REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL; | |
133 | ||
2b1fa9d3 | 134 | /* Configure I2C switch (PCA9543) to enable channel 0. */ |
6d0f6bcf JCPV |
135 | i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0; |
136 | if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0, | |
137 | CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) { | |
138 | printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR); | |
2b1fa9d3 HV |
139 | return 1; |
140 | } | |
141 | ||
264bbdd1 HV |
142 | /* Read Ethernet MAC address from EEPROM if available. */ |
143 | if (sffsdr_read_mac_address(eeprom_enetaddr)) | |
7b37a27e | 144 | davinci_sync_env_enetaddr(eeprom_enetaddr); |
2b1fa9d3 | 145 | |
2b1fa9d3 HV |
146 | return(0); |
147 | } |