[thirdparty/u-boot.git] / board / dhelectronics / dh_imx8mp / imx8mp_dhcom_pdk2.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2022 Marek Vasut <marex@denx.de>
 */

#include <common.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <dm.h>
#include <dt-bindings/clock/imx8mp-clock.h>
#include <env.h>
#include <env_internal.h>
#include <i2c_eeprom.h>
#include <linux/bitfield.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>

#include "lpddr4_timing.h"
#include "../common/dh_common.h"
#include "../common/dh_imx.h"

DECLARE_GLOBAL_DATA_PTR;

int mach_cpu_init(void)
{
	icache_enable();
	return 0;
}

int board_phys_sdram_size(phys_size_t *size)
{
	const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
	u8 memcfg = dh_get_memcfg();

	*size = (u64)memsz[memcfg] << 20ULL;

	return 0;
}

static int dh_imx8_setup_ethaddr(void)
{
	unsigned char enetaddr[6];

	if (dh_mac_is_in_env("ethaddr"))
		return 0;

	if (!dh_imx_get_mac_from_fuse(enetaddr))
		goto out;

	if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
		goto out;

	return -ENXIO;

out:
	return eth_env_set_enetaddr("ethaddr", enetaddr);
}

static int dh_imx8_setup_eth1addr(void)
{
	unsigned char enetaddr[6];

	if (dh_mac_is_in_env("eth1addr"))
		return 0;

	if (!dh_imx_get_mac_from_fuse(enetaddr))
		goto increment_out;

	if (!dh_get_mac_from_eeprom(enetaddr, "eeprom1"))
		goto out;

	/*
	 * Populate second ethernet MAC from first ethernet EEPROM with MAC
	 * address LSByte incremented by 1. This is only used on SoMs without
	 * second ethernet EEPROM, i.e. early prototypes.
	 */
	if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
		goto increment_out;

	return -ENXIO;

increment_out:
	enetaddr[5]++;

out:
	return eth_env_set_enetaddr("eth1addr", enetaddr);
}

int dh_setup_mac_address(void)
{
	int ret;

	ret = dh_imx8_setup_ethaddr();
	if (ret)
		printf("%s: Unable to setup ethaddr! ret = %d\n", __func__, ret);

	ret = dh_imx8_setup_eth1addr();
	if (ret)
		printf("%s: Unable to setup eth1addr! ret = %d\n", __func__, ret);

	return ret;
}

int board_init(void)
{
	return 0;
}

int board_late_init(void)
{
	dh_setup_mac_address();
	return 0;
}

enum env_location env_get_location(enum env_operation op, int prio)
{
	return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
}

static const char *iomuxc_compat = "fsl,imx8mp-iomuxc";
static const char *lan_compat = "ethernet-phy-id0007.c110";
static const char *ksz_compat = "ethernet-phy-id0022.1642";

static int dh_dt_patch_som_eqos(const void *fdt_blob)
{
	const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
		FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24);
	int mac_node, mdio_node, iomuxc_node, ksz_node, lan_node, subnode;
	const char *mac_compat = "nxp,imx8mp-dwmac-eqos";
	void *blob = (void *)fdt_blob;
	const fdt32_t *clk_prop;
	bool is_gigabit;
	u32 handle;
	u32 clk[6];

	setbits_le32(mux, IOMUX_CONFIG_SION);
	is_gigabit = !(readl(GPIO1_BASE_ADDR) & BIT(24));
	clrbits_le32(mux, IOMUX_CONFIG_SION);

	/* Adjust EQoS node for Gigabit KSZ9131RNXI or Fast LAN8740Ai PHY */
	mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
	if (mac_node < 0)
		return 0;

	mdio_node = fdt_first_subnode(blob, mac_node);
	if (mdio_node < 0)
		return 0;

	/* KSZ9131RNXI */
	ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat);
	if (ksz_node < 0)
		return 0;

	/* LAN8740Ai */
	lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
	if (lan_node < 0)
		return 0;

	iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat);
	if (iomuxc_node < 0)
		return 0;

	/*
	 * The code below adjusts the following DT properties:
	 * - assigned-clock-parents .. 125 MHz RGMII / 50 MHz RMII ref clock
	 * - assigned-clock-rates .... 125 MHz RGMII / 50 MHz RMII ref clock
	 * - phy-handle .............. KSZ9131RNXI RGMII / LAN8740Ai RMII
	 * - phy-mode ................ RGMII / RMII
	 * - pinctrl-0 ............... RGMII / RMII
	 * - PHY subnode status ...... "disabled"/"okay" per RGMII / RMII
	 */

	/* Perform all inplace changes first, string changes last. */
	clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL);
	if (!clk_prop)
		return 0;
	clk[0] = clk_prop[0];
	clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M);
	clk[2] = clk_prop[2];
	clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M);
	clk[4] = clk_prop[4];
	clk[5] = is_gigabit ? cpu_to_fdt32(IMX8MP_SYS_PLL2_125M) :
			      cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
	fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents",
			    clk, 6 * sizeof(u32));

	clk[0] = cpu_to_fdt32(0);
	clk[1] = cpu_to_fdt32(100000000);
	clk[2] = is_gigabit ? cpu_to_fdt32(125000000) :
			      cpu_to_fdt32(50000000);
	fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates",
			    clk, 3 * sizeof(u32));

	handle = fdt_get_phandle(blob, is_gigabit ? ksz_node : lan_node);
	fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle);

	fdt_for_each_subnode(subnode, blob, iomuxc_node) {
		if (!strstr(fdt_get_name(blob, subnode, NULL),
			    is_gigabit ? "eqos-rgmii" : "eqos-rmii"))
			continue;

		handle = fdt_get_phandle(blob, subnode);
		fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle);
		break;
	}

	fdt_setprop_string(blob, mac_node, "phy-mode",
			   is_gigabit ? "rgmii-id" : "rmii");

	mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
	mdio_node = fdt_first_subnode(blob, mac_node);
	ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat);
	fdt_setprop_string(blob, ksz_node, "status",
			   is_gigabit ? "okay" : "disabled");

	mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
	mdio_node = fdt_first_subnode(blob, mac_node);
	lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
	fdt_setprop_string(blob, lan_node, "status",
			   is_gigabit ? "disabled" : "okay");

	return 0;
}

static int dh_dt_patch_som_fec(const void *fdt_blob)
{
	const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
		FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10);
	int mac_node, mdio_node, iomuxc_node, lan_node, phy_node, subnode;
	const char *mac_compat = "fsl,imx8mp-fec";
	void *blob = (void *)fdt_blob;
	const fdt32_t *clk_prop;
	bool is_gigabit;
	u32 handle;
	u32 clk[8];

	setbits_le32(mux, IOMUX_CONFIG_SION);
	is_gigabit = !(readl(GPIO4_BASE_ADDR) & BIT(10));
	clrbits_le32(mux, IOMUX_CONFIG_SION);

	/* Test for non-default SoM with 100/Full PHY attached to FEC */
	if (is_gigabit)
		return 0;

	/* Adjust FEC node for Fast LAN8740Ai PHY */
	mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
	if (mac_node < 0)
		return 0;

	/* Optional PHY pointed to by phy-handle, possibly on carrier board */
	phy_node = fdtdec_lookup_phandle(blob, mac_node, "phy-handle");
	if (phy_node > 0) {
		fdt_setprop_string(blob, phy_node, "status", "disabled");
		mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
	}

	mdio_node = fdt_first_subnode(blob, mac_node);
	if (mdio_node < 0)
		return 0;

	/* LAN8740Ai */
	lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
	if (lan_node < 0)
		return 0;

	iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat);
	if (iomuxc_node < 0)
		return 0;

	/*
	 * The code below adjusts the following DT properties:
	 * - assigned-clock-parents .. 50 MHz RMII ref clock
	 * - assigned-clock-rates .... 50 MHz RMII ref clock
	 * - phy-handle .............. LAN8740Ai RMII
	 * - phy-mode ................ RMII
	 * - pinctrl-0 ............... RMII
	 * - PHY subnode status ...... "okay" for RMII PHY
	 */

	/* Perform all inplace changes first, string changes last. */
	clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL);
	if (!clk_prop)
		return 0;
	clk[0] = clk_prop[0];
	clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M);
	clk[2] = clk_prop[2];
	clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M);
	clk[4] = clk_prop[4];
	clk[5] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
	clk[6] = clk_prop[6];
	clk[7] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
	fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents",
			    clk, 8 * sizeof(u32));

	clk[0] = cpu_to_fdt32(0);
	clk[1] = cpu_to_fdt32(100000000);
	clk[2] = cpu_to_fdt32(50000000);
	clk[3] = cpu_to_fdt32(0);
	fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates",
			    clk, 4 * sizeof(u32));

	handle = fdt_get_phandle(blob, lan_node);
	fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle);

	fdt_for_each_subnode(subnode, blob, iomuxc_node) {
		if (!strstr(fdt_get_name(blob, subnode, NULL), "fec-rmii"))
			continue;

		handle = fdt_get_phandle(blob, subnode);
		fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle);
		break;
	}

	fdt_setprop_string(blob, mac_node, "phy-mode", "rmii");
	mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
	mdio_node = fdt_first_subnode(blob, mac_node);
	lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
	fdt_setprop_string(blob, lan_node, "status", "okay");

	return 0;
}

static int dh_dt_patch_som(const void *fdt_blob)
{
	int ret;

	/* Do nothing if not i.MX8MP DHCOM SoM */
	ret = fdt_node_check_compatible(fdt_blob, 0, "dh,imx8mp-dhcom-som");
	if (ret)
		return 0;

	ret = dh_dt_patch_som_eqos(fdt_blob);
	if (ret)
		return ret;

	return dh_dt_patch_som_fec(fdt_blob);
}

int fdtdec_board_setup(const void *fdt_blob)
{
	return dh_dt_patch_som(fdt_blob);
}
Commit	Line	Data
4d573d5c MV	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright 2022 Marek Vasut <marex@denx.de>
	4	*/
	5
	6	#include <common.h>
	7	#include <asm/arch/clock.h>
ef7ceb3e MV	8	#include <asm/mach-imx/iomux-v3.h>
ef7ceb3e MV	9	#include <asm/arch/imx8mp_pins.h>
4d573d5c MV	10	#include <asm/arch/sys_proto.h>
	11	#include <asm/io.h>
	12	#include <dm.h>
ef7ceb3e	13	#include <dt-bindings/clock/imx8mp-clock.h>
4d573d5c MV	14	#include <env.h>
	15	#include <env_internal.h>
	16	#include <i2c_eeprom.h>
ef7ceb3e	17	#include <linux/bitfield.h>
4d573d5c MV	18	#include <malloc.h>
	19	#include <net.h>
	20	#include <miiphy.h>
	21
	22	#include "lpddr4_timing.h"
4b238c2c PO	23	#include "../common/dh_common.h"
4b238c2c PO	24	#include "../common/dh_imx.h"
4d573d5c MV	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
	28	int mach_cpu_init(void)
	29	{
	30	icache_enable();
	31	return 0;
	32	}
	33
	34	int board_phys_sdram_size(phys_size_t *size)
	35	{
	36	const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
	37	u8 memcfg = dh_get_memcfg();
	38
	39	*size = (u64)memsz[memcfg] << 20ULL;
	40
	41	return 0;
	42	}
	43
4b238c2c	44	static int dh_imx8_setup_ethaddr(void)
4d573d5c MV	45	{
4d573d5c MV	46	unsigned char enetaddr[6];
4b238c2c PO	47
	48	if (dh_mac_is_in_env("ethaddr"))
	49	return 0;
	50
	51	if (!dh_imx_get_mac_from_fuse(enetaddr))
	52	goto out;
	53
	54	if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
	55	goto out;
	56
	57	return -ENXIO;
	58
	59	out:
	60	return eth_env_set_enetaddr("ethaddr", enetaddr);
	61	}
	62
	63	static int dh_imx8_setup_eth1addr(void)
	64	{
	65	unsigned char enetaddr[6];
	66
	67	if (dh_mac_is_in_env("eth1addr"))
	68	return 0;
	69
	70	if (!dh_imx_get_mac_from_fuse(enetaddr))
	71	goto increment_out;
	72
	73	if (!dh_get_mac_from_eeprom(enetaddr, "eeprom1"))
	74	goto out;
4d573d5c MV	75
	76	/*
	77	* Populate second ethernet MAC from first ethernet EEPROM with MAC
	78	* address LSByte incremented by 1. This is only used on SoMs without
	79	* second ethernet EEPROM, i.e. early prototypes.
	80	*/
4b238c2c PO	81	if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
4b238c2c PO	82	goto increment_out;
4d573d5c	83
4b238c2c	84	return -ENXIO;
4d573d5c	85
4b238c2c PO	86	increment_out:
	87	enetaddr[5]++;
	88
	89	out:
	90	return eth_env_set_enetaddr("eth1addr", enetaddr);
4d573d5c MV	91	}
4d573d5c MV	92
4b238c2c	93	int dh_setup_mac_address(void)
4d573d5c	94	{
4d573d5c MV	95	int ret;
4d573d5c MV	96
4b238c2c PO	97	ret = dh_imx8_setup_ethaddr();
	98	if (ret)
	99	printf("%s: Unable to setup ethaddr! ret = %d\n", __func__, ret);
4d573d5c	100
4b238c2c PO	101	ret = dh_imx8_setup_eth1addr();
	102	if (ret)
	103	printf("%s: Unable to setup eth1addr! ret = %d\n", __func__, ret);
4d573d5c	104
4b238c2c	105	return ret;
4d573d5c MV	106	}
	107
	108	int board_init(void)
	109	{
4d573d5c MV	110	return 0;
	111	}
	112
	113	int board_late_init(void)
	114	{
4b238c2c	115	dh_setup_mac_address();
4d573d5c MV	116	return 0;
	117	}
	118
	119	enum env_location env_get_location(enum env_operation op, int prio)
	120	{
	121	return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
	122	}
ef7ceb3e MV	123
	124	static const char *iomuxc_compat = "fsl,imx8mp-iomuxc";
	125	static const char *lan_compat = "ethernet-phy-id0007.c110";
	126	static const char *ksz_compat = "ethernet-phy-id0022.1642";
	127
	128	static int dh_dt_patch_som_eqos(const void *fdt_blob)
	129	{
	130	const void __iomem mux = (void __iomem )IOMUXC_BASE_ADDR +
	131	FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24);
	132	int mac_node, mdio_node, iomuxc_node, ksz_node, lan_node, subnode;
	133	const char *mac_compat = "nxp,imx8mp-dwmac-eqos";
	134	void blob = (void )fdt_blob;
	135	const fdt32_t *clk_prop;
	136	bool is_gigabit;
	137	u32 handle;
	138	u32 clk[6];
	139
	140	setbits_le32(mux, IOMUX_CONFIG_SION);
	141	is_gigabit = !(readl(GPIO1_BASE_ADDR) & BIT(24));
	142	clrbits_le32(mux, IOMUX_CONFIG_SION);
	143
	144	/* Adjust EQoS node for Gigabit KSZ9131RNXI or Fast LAN8740Ai PHY */
	145	mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
	146	if (mac_node < 0)
	147	return 0;
	148
	149	mdio_node = fdt_first_subnode(blob, mac_node);
	150	if (mdio_node < 0)
	151	return 0;
	152
	153	/* KSZ9131RNXI */
	154	ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat);
	155	if (ksz_node < 0)
	156	return 0;
	157
	158	/* LAN8740Ai */
	159	lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
	160	if (lan_node < 0)
	161	return 0;
	162
	163	iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat);
	164	if (iomuxc_node < 0)
	165	return 0;
	166
	167	/*
	168	* The code below adjusts the following DT properties:
	169	* - assigned-clock-parents .. 125 MHz RGMII / 50 MHz RMII ref clock
	170	* - assigned-clock-rates .... 125 MHz RGMII / 50 MHz RMII ref clock
	171	* - phy-handle .............. KSZ9131RNXI RGMII / LAN8740Ai RMII
	172	* - phy-mode ................ RGMII / RMII
	173	* - pinctrl-0 ............... RGMII / RMII
	174	* - PHY subnode status ...... "disabled"/"okay" per RGMII / RMII
	175	*/
	176
	177	/* Perform all inplace changes first, string changes last. */
	178	clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL);
	179	if (!clk_prop)
	180	return 0;
	181	clk[0] = clk_prop[0];
	182	clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M);
	183	clk[2] = clk_prop[2];
	184	clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M);
	185	clk[4] = clk_prop[4];
	186	clk[5] = is_gigabit ? cpu_to_fdt32(IMX8MP_SYS_PLL2_125M) :
187	cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
188	fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents",
189	clk, 6 * sizeof(u32));
190
191	clk[0] = cpu_to_fdt32(0);
192	clk[1] = cpu_to_fdt32(100000000);
193	clk[2] = is_gigabit ? cpu_to_fdt32(125000000) :
194	cpu_to_fdt32(50000000);
195	fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates",
196	clk, 3 * sizeof(u32));
197
198	handle = fdt_get_phandle(blob, is_gigabit ? ksz_node : lan_node);
199	fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle);
200
201	fdt_for_each_subnode(subnode, blob, iomuxc_node) {
202	if (!strstr(fdt_get_name(blob, subnode, NULL),
203	is_gigabit ? "eqos-rgmii" : "eqos-rmii"))
204	continue;
205
206	handle = fdt_get_phandle(blob, subnode);
207	fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle);
208	break;
209	}
210
211	fdt_setprop_string(blob, mac_node, "phy-mode",
212	is_gigabit ? "rgmii-id" : "rmii");
213
214	mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
215	mdio_node = fdt_first_subnode(blob, mac_node);
216	ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat);
217	fdt_setprop_string(blob, ksz_node, "status",
218	is_gigabit ? "okay" : "disabled");
219
220	mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
221	mdio_node = fdt_first_subnode(blob, mac_node);
222	lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
223	fdt_setprop_string(blob, lan_node, "status",
224	is_gigabit ? "disabled" : "okay");
225
226	return 0;
227	}
228
229	static int dh_dt_patch_som_fec(const void *fdt_blob)
230	{
231	const void __iomem mux = (void __iomem )IOMUXC_BASE_ADDR +
232	FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10);
233	int mac_node, mdio_node, iomuxc_node, lan_node, phy_node, subnode;
234	const char *mac_compat = "fsl,imx8mp-fec";
235	void blob = (void )fdt_blob;
236	const fdt32_t *clk_prop;
237	bool is_gigabit;
238	u32 handle;
239	u32 clk[8];
240
241	setbits_le32(mux, IOMUX_CONFIG_SION);
242	is_gigabit = !(readl(GPIO4_BASE_ADDR) & BIT(10));
243	clrbits_le32(mux, IOMUX_CONFIG_SION);
244
245	/* Test for non-default SoM with 100/Full PHY attached to FEC */
246	if (is_gigabit)
247	return 0;
248
249	/* Adjust FEC node for Fast LAN8740Ai PHY */
250	mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
251	if (mac_node < 0)
252	return 0;
253
254	/* Optional PHY pointed to by phy-handle, possibly on carrier board */
255	phy_node = fdtdec_lookup_phandle(blob, mac_node, "phy-handle");
256	if (phy_node > 0) {
257	fdt_setprop_string(blob, phy_node, "status", "disabled");
258	mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
259	}
260
261	mdio_node = fdt_first_subnode(blob, mac_node);
262	if (mdio_node < 0)
263	return 0;
264
265	/* LAN8740Ai */
266	lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
267	if (lan_node < 0)
268	return 0;
269
270	iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat);
271	if (iomuxc_node < 0)
272	return 0;
273
274	/*
275	* The code below adjusts the following DT properties:
276	* - assigned-clock-parents .. 50 MHz RMII ref clock
277	* - assigned-clock-rates .... 50 MHz RMII ref clock
278	* - phy-handle .............. LAN8740Ai RMII
279	* - phy-mode ................ RMII
280	* - pinctrl-0 ............... RMII
281	* - PHY subnode status ...... "okay" for RMII PHY
282	*/
283
284	/* Perform all inplace changes first, string changes last. */
285	clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL);
286	if (!clk_prop)
287	return 0;
288	clk[0] = clk_prop[0];
289	clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M);
290	clk[2] = clk_prop[2];
291	clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M);
292	clk[4] = clk_prop[4];
293	clk[5] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
294	clk[6] = clk_prop[6];
295	clk[7] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
296	fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents",
297	clk, 8 * sizeof(u32));
298
299	clk[0] = cpu_to_fdt32(0);
300	clk[1] = cpu_to_fdt32(100000000);
301	clk[2] = cpu_to_fdt32(50000000);
302	clk[3] = cpu_to_fdt32(0);
303	fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates",
304	clk, 4 * sizeof(u32));
305
306	handle = fdt_get_phandle(blob, lan_node);
307	fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle);
308
309	fdt_for_each_subnode(subnode, blob, iomuxc_node) {
310	if (!strstr(fdt_get_name(blob, subnode, NULL), "fec-rmii"))
311	continue;
312
313	handle = fdt_get_phandle(blob, subnode);
314	fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle);
315	break;
316	}
317
318	fdt_setprop_string(blob, mac_node, "phy-mode", "rmii");
319	mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
320	mdio_node = fdt_first_subnode(blob, mac_node);
321	lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
322	fdt_setprop_string(blob, lan_node, "status", "okay");
323
324	return 0;
325	}
326
327	static int dh_dt_patch_som(const void *fdt_blob)
328	{
329	int ret;
330
331	/* Do nothing if not i.MX8MP DHCOM SoM */
332	ret = fdt_node_check_compatible(fdt_blob, 0, "dh,imx8mp-dhcom-som");
333	if (ret)
334	return 0;
335
336	ret = dh_dt_patch_som_eqos(fdt_blob);
337	if (ret)
338	return ret;
339
340	return dh_dt_patch_som_fec(fdt_blob);
341	}
342
343	int fdtdec_board_setup(const void *fdt_blob)
344	{
345	return dh_dt_patch_som(fdt_blob);
346	}