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5c4fa9b4 GB |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. | |
7 | * | |
8 | * (C) Copyright 2005-2009 | |
9 | * Modified for InterControl digsyMTC MPC5200 board by | |
10 | * Frank Bodammer, GCD Hard- & Software GmbH, | |
11 | * frank.bodammer@gcd-solutions.de | |
12 | * | |
13 | * (C) Copyright 2009 | |
14 | * Grzegorz Bernacki, Semihalf, gjb@semihalf.com | |
15 | * | |
16 | * See file CREDITS for list of people who contributed to this | |
17 | * project. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License as | |
21 | * published by the Free Software Foundation; either version 2 of | |
22 | * the License, or (at your option) any later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, | |
25 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
27 | * GNU General Public License for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License | |
30 | * along with this program; if not, write to the Free Software | |
31 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
32 | * MA 02111-1307 USA | |
33 | */ | |
34 | ||
35 | #include <common.h> | |
36 | #include <mpc5xxx.h> | |
37 | #include <net.h> | |
38 | #include <pci.h> | |
39 | #include <asm/processor.h> | |
40 | #include <asm/io.h> | |
41 | #include "eeprom.h" | |
466f0137 HS |
42 | #if defined(CONFIG_DIGSY_REV5) |
43 | #include "is45s16800a2.h" | |
44 | #include <mtd/cfi_flash.h> | |
f3143134 | 45 | #include <flash.h> |
466f0137 | 46 | #else |
5c4fa9b4 | 47 | #include "is42s16800a-7t.h" |
466f0137 HS |
48 | #endif |
49 | #include <libfdt.h> | |
927d2cea | 50 | #include <fdt_support.h> |
5c4fa9b4 GB |
51 | |
52 | DECLARE_GLOBAL_DATA_PTR; | |
53 | ||
54 | extern int usb_cpu_init(void); | |
55 | ||
466f0137 HS |
56 | #if defined(CONFIG_DIGSY_REV5) |
57 | /* | |
58 | * The M29W128GH needs a specail reset command function, | |
59 | * details see the doc/README.cfi file | |
60 | */ | |
61 | void flash_cmd_reset(flash_info_t *info) | |
62 | { | |
63 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); | |
64 | } | |
65 | #endif | |
66 | ||
5c4fa9b4 GB |
67 | #ifndef CONFIG_SYS_RAMBOOT |
68 | static void sdram_start(int hi_addr) | |
69 | { | |
70 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | |
71 | long control = SDRAM_CONTROL | hi_addr_bit; | |
72 | ||
73 | /* unlock mode register */ | |
74 | out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); | |
75 | ||
76 | /* precharge all banks */ | |
77 | out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); | |
78 | ||
79 | /* auto refresh */ | |
80 | out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); | |
81 | ||
82 | /* set mode register */ | |
83 | out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); | |
84 | ||
85 | /* normal operation */ | |
86 | out_be32((void *)MPC5XXX_SDRAM_CTRL, control); | |
87 | } | |
88 | #endif | |
89 | ||
90 | /* | |
91 | * ATTENTION: Although partially referenced initdram does NOT make real use | |
92 | * use of CONFIG_SYS_SDRAM_BASE. The code does not work if | |
93 | * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. | |
94 | */ | |
95 | ||
96 | phys_size_t initdram(int board_type) | |
97 | { | |
98 | ulong dramsize = 0; | |
99 | ulong dramsize2 = 0; | |
100 | uint svr, pvr; | |
101 | #ifndef CONFIG_SYS_RAMBOOT | |
102 | ulong test1, test2; | |
103 | ||
104 | /* setup SDRAM chip selects */ | |
105 | out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */ | |
106 | out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ | |
107 | ||
108 | /* setup config registers */ | |
109 | out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); | |
110 | out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); | |
111 | ||
112 | /* find RAM size using SDRAM CS0 only */ | |
113 | sdram_start(0); | |
114 | test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); | |
115 | sdram_start(1); | |
116 | test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000); | |
117 | if (test1 > test2) { | |
118 | sdram_start(0); | |
119 | dramsize = test1; | |
120 | } else { | |
121 | dramsize = test2; | |
122 | } | |
123 | ||
124 | /* memory smaller than 1MB is impossible */ | |
125 | if (dramsize < (1 << 20)) | |
126 | dramsize = 0; | |
127 | ||
128 | /* set SDRAM CS0 size according to the amount of RAM found */ | |
129 | if (dramsize > 0) { | |
130 | out_be32((void *)MPC5XXX_SDRAM_CS0CFG, | |
131 | (0x13 + __builtin_ffs(dramsize >> 20) - 1)); | |
132 | } else { | |
133 | out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ | |
134 | } | |
135 | ||
136 | /* let SDRAM CS1 start right after CS0 */ | |
137 | out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C); | |
138 | ||
139 | /* find RAM size using SDRAM CS1 only */ | |
140 | test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), | |
141 | 0x08000000); | |
142 | dramsize2 = test1; | |
143 | ||
144 | /* memory smaller than 1MB is impossible */ | |
145 | if (dramsize2 < (1 << 20)) | |
146 | dramsize2 = 0; | |
147 | ||
148 | /* set SDRAM CS1 size according to the amount of RAM found */ | |
149 | if (dramsize2 > 0) { | |
150 | out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize | | |
151 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1))); | |
152 | } else { | |
153 | out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */ | |
154 | } | |
155 | ||
156 | #else /* CONFIG_SYS_RAMBOOT */ | |
157 | ||
158 | /* retrieve size of memory connected to SDRAM CS0 */ | |
159 | dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; | |
160 | if (dramsize >= 0x13) | |
161 | dramsize = (1 << (dramsize - 0x13)) << 20; | |
162 | else | |
163 | dramsize = 0; | |
164 | ||
165 | /* retrieve size of memory connected to SDRAM CS1 */ | |
166 | dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF; | |
167 | if (dramsize2 >= 0x13) | |
168 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; | |
169 | else | |
170 | dramsize2 = 0; | |
171 | ||
172 | #endif /* CONFIG_SYS_RAMBOOT */ | |
173 | ||
174 | /* | |
175 | * On MPC5200B we need to set the special configuration delay in the | |
176 | * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM | |
177 | * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: | |
178 | * | |
179 | * "The SDelay should be written to a value of 0x00000004. It is | |
180 | * required to account for changes caused by normal wafer processing | |
181 | * parameters." | |
182 | */ | |
183 | svr = get_svr(); | |
184 | pvr = get_pvr(); | |
185 | if ((SVR_MJREV(svr) >= 2) && | |
186 | (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) | |
187 | out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); | |
188 | ||
189 | return dramsize + dramsize2; | |
190 | } | |
191 | ||
192 | int checkboard(void) | |
193 | { | |
f0c0b3a9 WD |
194 | char buf[64]; |
195 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
5c4fa9b4 GB |
196 | |
197 | puts ("Board: InterControl digsyMTC"); | |
466f0137 HS |
198 | #if defined(CONFIG_DIGSY_REV5) |
199 | puts (" rev5"); | |
200 | #endif | |
f0c0b3a9 | 201 | if (i > 0) { |
5c4fa9b4 | 202 | puts(", "); |
f0c0b3a9 | 203 | puts(buf); |
5c4fa9b4 GB |
204 | } |
205 | putc('\n'); | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | int board_early_init_r(void) | |
211 | { | |
f1f66edf GB |
212 | #ifdef CONFIG_MPC52XX_SPI |
213 | struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT; | |
214 | #endif | |
5c4fa9b4 GB |
215 | /* |
216 | * Now, when we are in RAM, enable flash write access for detection | |
217 | * process. Note that CS_BOOT cannot be cleared when executing in | |
218 | * flash. | |
219 | */ | |
220 | /* disable CS_BOOT */ | |
221 | clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25)); | |
222 | /* enable CS1 */ | |
223 | setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17)); | |
224 | /* enable CS0 */ | |
225 | setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16)); | |
226 | ||
227 | #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) | |
228 | /* Low level USB init, required for proper kernel operation */ | |
229 | usb_cpu_init(); | |
230 | #endif | |
f1f66edf GB |
231 | #ifdef CONFIG_MPC52XX_SPI |
232 | /* GPT 6 Output Enable */ | |
233 | out_be32(&gpt[6].emsr, 0x00000034); | |
234 | /* GPT 7 Output Enable */ | |
235 | out_be32(&gpt[7].emsr, 0x00000034); | |
236 | #endif | |
237 | ||
5c4fa9b4 GB |
238 | return (0); |
239 | } | |
240 | ||
241 | void board_get_enetaddr (uchar * enet) | |
242 | { | |
243 | ushort read = 0; | |
244 | ushort addr_of_eth_addr = 0; | |
245 | ushort len_sys = 0; | |
246 | ushort len_sys_cfg = 0; | |
247 | ||
248 | /* check identification word */ | |
249 | eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2); | |
250 | if (read != EEPROM_IDENT) | |
251 | return; | |
252 | ||
253 | /* calculate offset of config area */ | |
254 | eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2); | |
255 | eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG, | |
256 | (uchar *)&len_sys_cfg, 2); | |
257 | addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1; | |
258 | if (addr_of_eth_addr >= EEPROM_LEN) | |
259 | return; | |
260 | ||
261 | eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6); | |
262 | } | |
263 | ||
264 | int misc_init_r(void) | |
265 | { | |
266 | uchar enetaddr[6]; | |
267 | ||
268 | if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { | |
269 | board_get_enetaddr(enetaddr); | |
270 | eth_setenv_enetaddr("ethaddr", enetaddr); | |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
276 | #ifdef CONFIG_PCI | |
277 | static struct pci_controller hose; | |
278 | ||
279 | extern void pci_mpc5xxx_init(struct pci_controller *); | |
280 | ||
281 | void pci_init_board(void) | |
282 | { | |
283 | pci_mpc5xxx_init(&hose); | |
284 | } | |
285 | #endif | |
286 | ||
287 | #ifdef CONFIG_CMD_IDE | |
288 | ||
289 | #ifdef CONFIG_IDE_RESET | |
290 | ||
291 | void init_ide_reset(void) | |
292 | { | |
293 | debug ("init_ide_reset\n"); | |
294 | ||
295 | /* set gpio output value to 1 */ | |
296 | setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); | |
297 | /* open drain output */ | |
298 | setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); | |
299 | /* direction output */ | |
300 | setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); | |
301 | /* enable gpio */ | |
302 | setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); | |
303 | ||
304 | } | |
305 | ||
306 | void ide_set_reset(int idereset) | |
307 | { | |
308 | debug ("ide_reset(%d)\n", idereset); | |
309 | ||
310 | /* set gpio output value to 0 */ | |
311 | clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); | |
312 | /* open drain output */ | |
313 | setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); | |
314 | /* direction output */ | |
315 | setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); | |
316 | /* enable gpio */ | |
317 | setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); | |
318 | ||
319 | udelay(10000); | |
320 | ||
321 | /* set gpio output value to 1 */ | |
322 | setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25)); | |
323 | /* open drain output */ | |
324 | setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25)); | |
325 | /* direction output */ | |
326 | setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25)); | |
327 | /* enable gpio */ | |
328 | setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25)); | |
329 | } | |
330 | #endif /* CONFIG_IDE_RESET */ | |
466f0137 | 331 | #endif /* CONFIG_CMD_IDE */ |
5c4fa9b4 GB |
332 | |
333 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) | |
466f0137 HS |
334 | static void ft_delete_node(void *fdt, const char *compat) |
335 | { | |
336 | int off = -1; | |
337 | int ret; | |
338 | ||
339 | off = fdt_node_offset_by_compatible(fdt, -1, compat); | |
340 | if (off < 0) { | |
341 | printf("Could not find %s node.\n", compat); | |
342 | return; | |
343 | } | |
344 | ||
345 | ret = fdt_del_node(fdt, off); | |
346 | if (ret < 0) | |
347 | printf("Could not delete %s node.\n", compat); | |
348 | } | |
349 | #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) | |
350 | static void ft_adapt_flash_base(void *blob) | |
351 | { | |
352 | flash_info_t *dev = &flash_info[0]; | |
353 | int off; | |
354 | struct fdt_property *prop; | |
355 | int len; | |
356 | u32 *reg, *reg2; | |
357 | ||
358 | off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb"); | |
359 | if (off < 0) { | |
360 | printf("Could not find fsl,mpc5200b-lpb node.\n"); | |
361 | return; | |
362 | } | |
363 | ||
364 | /* found compatible property */ | |
365 | prop = fdt_get_property_w(blob, off, "ranges", &len); | |
366 | if (prop) { | |
367 | reg = reg2 = (u32 *)&prop->data[0]; | |
368 | ||
369 | reg[2] = dev->start[0]; | |
370 | reg[3] = dev->size; | |
371 | fdt_setprop(blob, off, "ranges", reg2, len); | |
372 | } else | |
373 | printf("Could not find ranges\n"); | |
374 | } | |
375 | ||
376 | extern ulong flash_get_size (phys_addr_t base, int banknum); | |
377 | ||
378 | /* Update the Flash Baseaddr settings */ | |
379 | int update_flash_size (int flash_size) | |
380 | { | |
381 | volatile struct mpc5xxx_mmap_ctl *mm = | |
382 | (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR; | |
383 | flash_info_t *dev; | |
384 | int i; | |
385 | int size = 0; | |
386 | unsigned long base = 0x0; | |
387 | u32 *cs_reg = (u32 *)&mm->cs0_start; | |
388 | ||
389 | for (i = 0; i < 2; i++) { | |
390 | dev = &flash_info[i]; | |
391 | ||
392 | if (dev->size) { | |
393 | /* calculate new base addr for this chipselect */ | |
394 | base -= dev->size; | |
395 | out_be32(cs_reg, START_REG(base)); | |
396 | cs_reg++; | |
397 | out_be32(cs_reg, STOP_REG(base, dev->size)); | |
398 | cs_reg++; | |
399 | /* recalculate the sectoraddr in the cfi driver */ | |
400 | size += flash_get_size(base, i); | |
401 | } | |
402 | } | |
f3143134 | 403 | flash_protect_default(); |
466f0137 HS |
404 | gd->bd->bi_flashstart = base; |
405 | return 0; | |
406 | } | |
407 | #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */ | |
408 | ||
5c4fa9b4 GB |
409 | void ft_board_setup(void *blob, bd_t *bd) |
410 | { | |
1b41493d HS |
411 | int phy_addr = CONFIG_PHY_ADDR; |
412 | char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0"; | |
413 | ||
5c4fa9b4 | 414 | ft_cpu_setup(blob, bd); |
466f0137 HS |
415 | /* |
416 | * There are 2 RTC nodes in the DTS, so remove | |
417 | * the unneeded node here. | |
418 | */ | |
419 | #if defined(CONFIG_DIGSY_REV5) | |
420 | ft_delete_node(blob, "dallas,ds1339"); | |
421 | #else | |
422 | ft_delete_node(blob, "mc,rv3029c2"); | |
423 | #endif | |
424 | #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) | |
927d2cea HS |
425 | #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE |
426 | /* Update reg property in all nor flash nodes too */ | |
427 | fdt_fixup_nor_flash_size(blob); | |
428 | #endif | |
466f0137 HS |
429 | ft_adapt_flash_base(blob); |
430 | #endif | |
1b41493d HS |
431 | /* fix up the phy address */ |
432 | do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0); | |
5c4fa9b4 GB |
433 | } |
434 | #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |