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f4b7532f JT |
1 | /* |
2 | * Copyright (C) 2016 Amarula Solutions B.V. | |
3 | * Copyright (C) 2016 Engicam S.r.l. | |
4 | * Author: Jagan Teki <jagan@amarulasolutions.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
4bbd4059 | 10 | #include <mmc.h> |
f4b7532f JT |
11 | |
12 | #include <asm/io.h> | |
13 | #include <asm/gpio.h> | |
14 | #include <linux/sizes.h> | |
15 | ||
16 | #include <asm/arch/clock.h> | |
58413366 | 17 | #include <asm/arch/crm_regs.h> |
f4b7532f JT |
18 | #include <asm/arch/iomux.h> |
19 | #include <asm/arch/mx6-pins.h> | |
20 | #include <asm/arch/sys_proto.h> | |
552a848e SB |
21 | #include <asm/mach-imx/iomux-v3.h> |
22 | #include <asm/mach-imx/video.h> | |
f4b7532f | 23 | |
ac880e77 JT |
24 | #include "../common/board.h" |
25 | ||
f4b7532f JT |
26 | DECLARE_GLOBAL_DATA_PTR; |
27 | ||
023ff2f7 JT |
28 | #ifdef CONFIG_NAND_MXS |
29 | ||
30 | #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) | |
31 | #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ | |
32 | PAD_CTL_SRE_FAST) | |
33 | #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) | |
34 | ||
35 | iomux_v3_cfg_t gpmi_pads[] = { | |
36 | IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
37 | IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
38 | IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
39 | IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), | |
40 | IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
41 | IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
42 | IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
43 | IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
44 | IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
45 | IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
46 | IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
47 | IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
48 | IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
49 | IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
50 | IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
51 | }; | |
52 | ||
ac880e77 | 53 | void setup_gpmi_nand(void) |
023ff2f7 JT |
54 | { |
55 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
56 | ||
57 | /* config gpmi nand iomux */ | |
58 | SETUP_IOMUX_PADS(gpmi_pads); | |
59 | ||
60 | /* gate ENFC_CLK_ROOT clock first,before clk source switch */ | |
61 | clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
62 | ||
63 | /* config gpmi and bch clock to 100 MHz */ | |
64 | clrsetbits_le32(&mxc_ccm->cs2cdr, | |
65 | MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | | |
66 | MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | | |
67 | MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, | |
68 | MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | | |
69 | MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | | |
70 | MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); | |
71 | ||
72 | /* enable ENFC_CLK_ROOT clock */ | |
73 | setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
74 | ||
75 | /* enable gpmi and bch clock gating */ | |
76 | setbits_le32(&mxc_ccm->CCGR4, | |
77 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
78 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
79 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
80 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
81 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); | |
82 | ||
83 | /* enable apbh clock gating */ | |
84 | setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); | |
85 | } | |
86 | #endif | |
87 | ||
ca7463c9 JT |
88 | #if defined(CONFIG_VIDEO_IPUV3) |
89 | static iomux_v3_cfg_t const rgb_pads[] = { | |
90 | IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), | |
91 | IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), | |
92 | IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), | |
93 | IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), | |
94 | IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), | |
95 | IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), | |
96 | IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), | |
97 | IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), | |
98 | IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), | |
99 | IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), | |
100 | IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), | |
101 | IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), | |
102 | IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), | |
103 | IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), | |
104 | IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), | |
105 | IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), | |
106 | IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), | |
107 | IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), | |
108 | IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), | |
109 | IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), | |
110 | IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), | |
111 | IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), | |
112 | }; | |
113 | ||
114 | static void enable_rgb(struct display_info_t const *dev) | |
115 | { | |
116 | SETUP_IOMUX_PADS(rgb_pads); | |
117 | } | |
118 | ||
119 | struct display_info_t const displays[] = { | |
120 | { | |
121 | .bus = -1, | |
122 | .addr = 0, | |
123 | .pixfmt = IPU_PIX_FMT_RGB666, | |
124 | .detect = NULL, | |
125 | .enable = enable_rgb, | |
126 | .mode = { | |
127 | .name = "Amp-WD", | |
128 | .refresh = 60, | |
129 | .xres = 800, | |
130 | .yres = 480, | |
131 | .pixclock = 30000, | |
132 | .left_margin = 30, | |
133 | .right_margin = 30, | |
134 | .upper_margin = 5, | |
135 | .lower_margin = 5, | |
136 | .hsync_len = 64, | |
137 | .vsync_len = 20, | |
138 | .sync = FB_SYNC_EXT, | |
139 | .vmode = FB_VMODE_NONINTERLACED | |
140 | } | |
141 | }, | |
142 | }; | |
143 | ||
144 | size_t display_count = ARRAY_SIZE(displays); | |
145 | ||
ac880e77 | 146 | void setup_display(void) |
ca7463c9 JT |
147 | { |
148 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
149 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
150 | int reg; | |
151 | ||
152 | enable_ipu_clock(); | |
153 | ||
154 | /* Turn on LDB0,IPU,IPU DI0 clocks */ | |
155 | reg = __raw_readl(&mxc_ccm->CCGR3); | |
156 | reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff); | |
157 | writel(reg, &mxc_ccm->CCGR3); | |
158 | ||
159 | /* set LDB0, LDB1 clk select to 011/011 */ | |
160 | reg = readl(&mxc_ccm->cs2cdr); | |
161 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | | |
162 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); | |
163 | reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | | |
164 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); | |
165 | writel(reg, &mxc_ccm->cs2cdr); | |
166 | ||
167 | reg = readl(&mxc_ccm->cscmr2); | |
168 | reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; | |
169 | writel(reg, &mxc_ccm->cscmr2); | |
170 | ||
171 | reg = readl(&mxc_ccm->chsccdr); | |
172 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << | |
173 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); | |
174 | writel(reg, &mxc_ccm->chsccdr); | |
175 | ||
176 | reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | | |
177 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | | |
178 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | | |
179 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | | |
180 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | | |
181 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | | |
182 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | | |
183 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | | |
184 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; | |
185 | writel(reg, &iomux->gpr[2]); | |
186 | ||
187 | reg = readl(&iomux->gpr[3]); | |
188 | reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | | |
189 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << | |
190 | IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); | |
191 | writel(reg, &iomux->gpr[3]); | |
192 | } | |
193 | #endif /* CONFIG_VIDEO_IPUV3 */ | |
194 | ||
f9247569 | 195 | void setenv_fdt_file(void) |
98f56610 | 196 | { |
6f1f3f59 | 197 | if (is_mx6dq()) |
382bee57 | 198 | env_set("fdt_file", "imx6q-icore.dtb"); |
6f1f3f59 | 199 | else if(is_mx6dl() || is_mx6solo()) |
382bee57 | 200 | env_set("fdt_file", "imx6dl-icore.dtb"); |
98f56610 JT |
201 | } |
202 | ||
f4b7532f | 203 | #ifdef CONFIG_SPL_BUILD |
f160c5c8 JT |
204 | /* MMC board initialization is needed till adding DM support in SPL */ |
205 | #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) | |
206 | #include <mmc.h> | |
207 | #include <fsl_esdhc.h> | |
208 | ||
209 | #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
210 | PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ | |
211 | PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
212 | ||
213 | static iomux_v3_cfg_t const usdhc1_pads[] = { | |
214 | IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
215 | IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
216 | IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
217 | IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
218 | IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
219 | IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
220 | IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ | |
221 | }; | |
222 | ||
223 | #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) | |
224 | ||
225 | struct fsl_esdhc_cfg usdhc_cfg[1] = { | |
226 | {USDHC1_BASE_ADDR, 0, 4}, | |
227 | }; | |
228 | ||
229 | int board_mmc_getcd(struct mmc *mmc) | |
230 | { | |
231 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
232 | int ret = 0; | |
233 | ||
234 | switch (cfg->esdhc_base) { | |
235 | case USDHC1_BASE_ADDR: | |
236 | ret = !gpio_get_value(USDHC1_CD_GPIO); | |
237 | break; | |
238 | } | |
239 | ||
240 | return ret; | |
241 | } | |
242 | ||
243 | int board_mmc_init(bd_t *bis) | |
244 | { | |
245 | int i, ret; | |
246 | ||
247 | /* | |
248 | * According to the board_mmc_init() the following map is done: | |
249 | * (U-boot device node) (Physical Port) | |
250 | * mmc0 USDHC1 | |
251 | */ | |
252 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { | |
253 | switch (i) { | |
254 | case 0: | |
255 | SETUP_IOMUX_PADS(usdhc1_pads); | |
256 | gpio_direction_input(USDHC1_CD_GPIO); | |
257 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); | |
258 | break; | |
259 | default: | |
260 | printf("Warning - USDHC%d controller not supporting\n", | |
261 | i + 1); | |
262 | return 0; | |
263 | } | |
264 | ||
265 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); | |
266 | if (ret) { | |
267 | printf("Warning: failed to initialize mmc dev %d\n", i); | |
268 | return ret; | |
269 | } | |
270 | } | |
271 | ||
272 | return 0; | |
273 | } | |
274 | #endif | |
275 | ||
bc1fe900 JT |
276 | #ifdef CONFIG_SPL_LOAD_FIT |
277 | int board_fit_config_name_match(const char *name) | |
278 | { | |
279 | if (is_mx6dq() && !strcmp(name, "imx6q-icore")) | |
280 | return 0; | |
281 | else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore")) | |
282 | return 0; | |
283 | else | |
284 | return -1; | |
285 | } | |
286 | #endif | |
d8de3c73 | 287 | #endif /* CONFIG_SPL_BUILD */ |